*.o
-*.ko
\ No newline at end of file
+*.ko
+*.rc
+*/bin/*
\ No newline at end of file
/*
- * unipi_common.h
+ * UniPi Neuron tty serial driver - Copyright (C) 2018 UniPi Technologies
+ * Author: Tomas Knot <tomasknot@gmail.com>
+ *
+ * Based on the SC16IS7xx driver by Jon Ringle <jringle@gridpoint.com>,
+ * which was in turn based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * Created on: 26 Feb 2018
- * Author: Tom Knot <knot@faster.cz>
*/
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_COMMON_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_COMMON_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
/***************
* Definitions *
***************/
-#define NEURONSPI_SCHED_REQUIRED 0 // Older kernels do not require sched/types to be specifically imported
+#define NEURONSPI_SCHED_REQUIRED 0 // Older kernels do not require sched/types to be specifically imported
#define NEURONSPI_MAJOR_VERSIONSTRING "Development Beta Version 0.02:12:02:2018"
#define NEURONSPI_MAX_DEVS 3
#define NEURONSPI_DETAILED_DEBUG 0
#define NEURONSPI_LAST_TRANSFER_DELAY 40
-
#define NEURON_DEVICE_NAME "neuronspi"
#define NEURON_DEVICE_CLASS "modbus_spi"
#define NEURON_DRIVER_NAME "NEURONSPI"
#define NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(X) ((((X) + 15) >> 4) << 1)
+/********************
+ * Module Constants *
+ ********************/
+
#define NEURONSPI_NO_INTERRUPT_MODELS_LEN 3
static const u16 NEURONSPI_NO_INTERRUPT_MODELS[NEURONSPI_NO_INTERRUPT_MODELS_LEN] = {
0xb10, 0xc10, 0xf10
};
+/*******************
+ * Data Structures *
+ *******************/
+
enum neuron_str_attribute_type {
NEURON_SATTR_MODEL,
NEURON_SATTR_EEPROM,
u8 p_count;
};
-
// Instantiated once
struct neuronspi_char_driver
{
struct device* dev;
};
-
// Instantiated once per SPI device
struct neuronspi_driver_data
{
spinlock_t lock;
};
-extern struct mutex neuronspi_master_mutex;
-
struct neuronspi_file_data
{
struct spi_device** spi_device;
u32 size;
};
+/*********************
+ * Data Declarations *
+ *********************/
+
+extern struct mutex neuronspi_master_mutex;
extern struct neuronspi_char_driver neuronspi_cdrv;
extern struct spinlock* neuronspi_spi_w_spinlock;
+extern struct spi_device* neuronspi_s_dev[NEURONSPI_MAX_DEVS];
+extern struct task_struct *neuronspi_invalidate_thread;
+
extern u8 neuronspi_spi_w_flag;
extern u8 neuronspi_probe_count;
extern int neuronspi_model_id;
extern spinlock_t neuronspi_probe_spinlock;
-extern struct spi_device* neuronspi_s_dev[NEURONSPI_MAX_DEVS];
-extern struct task_struct *neuronspi_invalidate_thread;
#endif /* MODULES_NEURON_SPI_SRC_UNIPI_COMMON_H_ */
*
*/
+/************
+ * Includes *
+ ************/
+
#include "unipi_gpio.h"
#include "unipi_spi.h"
+/************************
+ * Non-static Functions *
+ ************************/
+
int neuronspi_gpio_di_direction_input(struct gpio_chip *chip, unsigned offset) {
return 0;
}
+
int neuronspi_gpio_di_direction_output(struct gpio_chip *chip, unsigned offset, int value) {
return -EINVAL;
}
+
int neuronspi_gpio_di_get(struct gpio_chip *chip, unsigned offset) {
struct neuronspi_di_driver *n_di = gpiochip_get_data(chip);
struct spi_device *spi = n_di->spi;
int neuronspi_gpio_do_direction_output(struct gpio_chip *chip, unsigned offset, int value) {
return 0;
}
+
void neuronspi_gpio_do_set(struct gpio_chip *chip, unsigned offset, int value) {
struct neuronspi_do_driver *n_do = gpiochip_get_data(chip);
struct spi_device *spi = n_do->spi;
int neuronspi_gpio_ro_direction_output(struct gpio_chip *chip, unsigned offset, int value) {
return 0;
}
+
void neuronspi_gpio_ro_set(struct gpio_chip *chip, unsigned offset, int value) {
struct neuronspi_ro_driver *n_ro = gpiochip_get_data(chip);
struct spi_device *spi = n_ro->spi;
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_GPIO_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_GPIO_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include "unipi_common.h"
+/*************************
+ * Function Declarations *
+ *************************/
+
int neuronspi_gpio_di_direction_input(struct gpio_chip *chip, unsigned offset);
int neuronspi_gpio_di_direction_output(struct gpio_chip *chip, unsigned offset, int value);
int neuronspi_gpio_di_get(struct gpio_chip *chip, unsigned offset);
*
*/
+/************
+ * Includes *
+ ************/
+
#include "unipi_iio.h"
#include "unipi_spi.h"
+/************************
+ * Non-static Functions *
+ ************************/
int neuronspi_iio_stm_ai_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask) {
struct neuronspi_stm_ai_data *ai_data = iio_priv(indio_dev);
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_IIO_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_IIO_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include "unipi_common.h"
+/*************************
+ * Function Declarations *
+ *************************/
+
int neuronspi_iio_stm_ai_read_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask);
int neuronspi_iio_stm_ao_read_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask);
int neuronspi_iio_stm_ao_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask);
/*
- * unipi_misc.c
+ * UniPi Neuron tty serial driver - Copyright (C) 2018 UniPi Technologies
+ * Author: Tomas Knot <tomasknot@gmail.com>
+ *
+ * Based on the SC16IS7xx driver by Jon Ringle <jringle@gridpoint.com>,
+ * which was in turn based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * Created on: 26 Feb 2018
- * Author: Tom Knot <knot@faster.cz>
*/
+/************
+ * Includes *
+ ************/
+
#include "unipi_misc.h"
#include "unipi_spi.h"
+/************************
+ * Non-static Functions *
+ ************************/
+
void neuronspi_led_proc(struct kthread_work *ws)
{
struct neuronspi_led_driver *led = to_led_driver(ws, led_work);
/*
- * unipi_misc.h
+ * UniPi Neuron tty serial driver - Copyright (C) 2018 UniPi Technologies
+ * Author: Tomas Knot <tomasknot@gmail.com>
+ *
+ * Based on the SC16IS7xx driver by Jon Ringle <jringle@gridpoint.com>,
+ * which was in turn based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * Created on: 26 Feb 2018
- * Author: Tom Knot <knot@faster.cz>
*/
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_MISC_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_MISC_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include "unipi_common.h"
+/*************************
+ * Function Declarations *
+ *************************/
void neuronspi_led_proc(struct kthread_work *ws);
void neuronspi_led_set_brightness(struct led_classdev *ldev, enum led_brightness brightness);
/*
- * unipi_platform.c
+ * UniPi Neuron tty serial driver - Copyright (C) 2018 UniPi Technologies
+ * Author: Tomas Knot <tomasknot@gmail.com>
+ *
+ * Based on the SC16IS7xx driver by Jon Ringle <jringle@gridpoint.com>,
+ * which was in turn based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * Created on: 23 Feb 2018
- * Author: Tom Knot <knot@faster.cz>
*/
+/************
+ * Includes *
+ ************/
#include "unipi_platform.h"
#include "unipi_spi.h"
#include "unipi_common.h"
-struct platform_device *neuron_plc_dev;
-
-/*********************
- * Board Definitions *
- *********************/
+/***************************
+ * Static Data Definitions *
+ ***************************/
// B_1000 (S103)
#define NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE 57
}
struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION};
-/*********************
- * Model Definitions *
- *********************/
+/********************
+ * Data Definitions *
+ ********************/
+
+struct platform_device *neuron_plc_dev;
struct neuronspi_board_combination NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE] = {
NEURONSPI_BOARD_B1000_HW_DEFINITION
.combination_count = 3, .combinations = NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD}
};
+/************************
+ * Non-static Functions *
+ ************************/
+
s32 neuronspi_regmap_invalidate(void *data)
{
int i;
}
}
-int neuronspi_regmap_hw_reg_read(void *context, unsigned int reg, unsigned int *val) {
+int neuronspi_regmap_hw_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
struct spi_device *spi = context;
struct neuronspi_driver_data *n_spi = spi_get_drvdata(spi);
u8 *inp_buf;
return 0;
}
-int neuronspi_regmap_hw_write(void *context, const void *data, size_t count) {
+int neuronspi_regmap_hw_write(void *context, const void *data, size_t count)
+{
BUG_ON(count < 1);
return neuronspi_regmap_hw_gather_write(context, data, 1, data + 1, count - 1);
}
-int neuronspi_regmap_hw_reg_write(void *context, unsigned int reg, unsigned int val) {
+int neuronspi_regmap_hw_reg_write(void *context, unsigned int reg, unsigned int val)
+{
struct spi_device *spi = context;
struct neuronspi_driver_data *n_spi = spi_get_drvdata(spi);
u8 *inp_buf;
return 0;
}
-int neuronspi_regmap_hw_gather_write(void *context, const void *reg, size_t reg_size, const void *val, size_t val_size) {
+int neuronspi_regmap_hw_gather_write(void *context, const void *reg, size_t reg_size, const void *val, size_t val_size)
+{
u16 *mb_reg_buf = (u16*)reg;
u32 *mb_val_buf = (u32*)val;
struct spi_device *spi = context;
/*
- * unipi_platform.h
+ * UniPi Neuron tty serial driver - Copyright (C) 2018 UniPi Technologies
+ * Author: Tomas Knot <tomasknot@gmail.com>
+ *
+ * Based on the SC16IS7xx driver by Jon Ringle <jringle@gridpoint.com>,
+ * which was in turn based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * Created on: 23 Feb 2018
- * Author: Tom Knot <knot@faster.cz>
*/
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_PLATFORM_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_PLATFORM_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include "unipi_common.h"
-/********************************
- * HW Constants Data Structures *
- ********************************/
+/*******************
+ * Data Structures *
+ *******************/
struct neuronspi_board_entry {
u16 index;
struct neuronspi_board_combination *combinations;
};
+/***************
+ * Definitions *
+ ***************/
-/******************
- * HW Definitions *
- ******************/
-// Lower Boards:
+// Lower Boards
#define NEURONSPI_BOARD_LOWER_B1000_ID 0
#define NEURONSPI_BOARD_LOWER_E8DI8RO_ID 1
#define NEURONSPI_BOARD_LOWER_E14RO_ID 2
#define NEURONSPI_BOARD_LOWER_B485_ID 13
#define NEURONSPI_BOARD_LOWER_E4LIGHT_ID 14
-
-// Upper Boards:
+// Upper Boards
#define NEURONSPI_BOARD_UPPER_NONE_ID 0
#define NEURONSPI_BOARD_UPPER_P11DIR485_ID 1
#define NEURONSPI_BOARD_UPPER_U14RO_ID 2
#define NEURONSPI_BOARD_UPPER_P6DI5RO_ID 4
#define NEURONSPI_BOARD_UPPER_U6DI5RO_ID 5
-// Register function codes:
+// Register function codes
+// Digital Input Functions
#define NEURONSPI_FUNGROUP_DI 0
#define NEURONSPI_REGFUN_DI_READ 0 | NEURONSPI_FUNGROUP_DI << 8
#define NEURONSPI_REGFUN_DI_COUNTER_LOWER 1 | NEURONSPI_FUNGROUP_DI << 8
#define NEURONSPI_REGFUN_DS_POLARITY 5 | NEURONSPI_FUNGROUP_DI << 8
#define NEURONSPI_REGFUN_DS_TOGGLE 6 | NEURONSPI_FUNGROUP_DI << 8
+// Digital Output Functions
#define NEURONSPI_FUNGROUP_DO 1
#define NEURONSPI_REGFUN_DO_RW 0 | NEURONSPI_FUNGROUP_DO << 8
+// B1000 Analog Output Functions
#define NEURONSPI_FUNGROUP_AO_BRAIN 2
#define NEURONSPI_REGFUN_AO_BRAIN 0 | NEURONSPI_FUNGROUP_AO_BRAIN << 8
#define NEURONSPI_REGFUN_AO_BRAIN_MODE 1 | NEURONSPI_FUNGROUP_AO_BRAIN << 8
#define NEURONSPI_REGFUN_AO_BRAIN_I_ERR 4 | NEURONSPI_FUNGROUP_AO_BRAIN << 8
#define NEURONSPI_REGFUN_AO_BRAIN_I_OFF 5 | NEURONSPI_FUNGROUP_AO_BRAIN << 8
+// B1000 Analog Input Functions
#define NEURONSPI_FUNGROUP_AI_BRAIN 3
#define NEURONSPI_REGFUN_AI_BRAIN 0 | NEURONSPI_FUNGROUP_AI_BRAIN << 8
#define NEURONSPI_REGFUN_AIO_BRAIN 1 | NEURONSPI_FUNGROUP_AI_BRAIN << 8
#define NEURONSPI_REGFUN_AIO_BRAIN_ERR 7 | NEURONSPI_FUNGROUP_AI_BRAIN << 8
#define NEURONSPI_REGFUN_AIO_BRAIN_OFF 8 | NEURONSPI_FUNGROUP_AI_BRAIN << 8
+// System Functions
#define NEURONSPI_FUNGROUP_SYSTEM 4
#define NEURONSPI_REGFUN_V_REF_INT 0 | NEURONSPI_FUNGROUP_SYSTEM << 8
#define NEURONSPI_REGFUN_V_REF_INP 1 | NEURONSPI_FUNGROUP_SYSTEM << 8
#define NEURONSPI_REGFUN_INTERRUPTS 10 | NEURONSPI_FUNGROUP_SYSTEM << 8
#define NEURONSPI_REGFUN_NONE_TEST 11 | NEURONSPI_FUNGROUP_SYSTEM << 8
+// Watchdog Functions
#define NEURONSPI_FUNGROUP_MWD 5
#define NEURONSPI_REGFUN_MWD_TO 0 | NEURONSPI_FUNGROUP_MWD << 8
#define NEURONSPI_REGFUN_MWD_STATUS 1 | NEURONSPI_FUNGROUP_MWD << 8
+// PWM Functions
#define NEURONSPI_FUNGROUP_PWM 6
#define NEURONSPI_REGFUN_PWM_DUTY 0 | NEURONSPI_FUNGROUP_PWM << 8
#define NEURONSPI_REGFUN_PWM_PRESCALE 1 | NEURONSPI_FUNGROUP_PWM << 8
#define NEURONSPI_REGFUN_PWM_CYCLE 2 | NEURONSPI_FUNGROUP_PWM << 8
-
+// UART Functions
#define NEURONSPI_FUNGROUP_RS485 7
#define NEURONSPI_REGFUN_TX_QUEUE_LEN 0 | NEURONSPI_FUNGROUP_RS485 << 8
#define NEURONSPI_REGFUN_RS485_CONFIG 1 | NEURONSPI_FUNGROUP_RS485 << 8
#define NEURONSPI_REGFUN_RS485_ADDRESS 2 | NEURONSPI_FUNGROUP_RS485 << 8
+// Secondary Analog Output Functions
#define NEURONSPI_FUNGROUP_AO_VER2 8
#define NEURONSPI_REGFUN_AO_VER2_RW 0 | NEURONSPI_FUNGROUP_AO_VER2 << 8
+// Secondary Analog Input Functions
#define NEURONSPI_FUNGROUP_AI_VER2 9
#define NEURONSPI_REGFUN_AI_VER2_READ_LOWER 0 | NEURONSPI_FUNGROUP_AI_VER2 << 8
#define NEURONSPI_REGFUN_AI_VER2_READ_UPPER 0 | NEURONSPI_FUNGROUP_AI_VER2 << 8
#define NEURONSPI_REGFUN_AI_VER2_MODE 1 | NEURONSPI_FUNGROUP_AI_VER2 << 8
-// Register access flags:
+// Register access flags
#define NEURONSPI_REGFLAG_ACC_NEVER 0
#define NEURONSPI_REGFLAG_ACC_AFAP 0x1 << 16
#define NEURONSPI_REGFLAG_ACC_10HZ 0x2 << 16
#define NEURONSPI_REGFLAG_ACC_15MIN 0x6 << 16
#define NEURONSPI_REGFLAG_ACC_ONCE 0x7 << 16
-// Register system flags:
+// Register system flags
#define NEURONSPI_REGFLAG_SYS_READ_ONLY 0x10 << 24
+// IIO Modes
#define NEURONSPI_IIO_AI_STM_MODE_VOLTAGE 0x0
#define NEURONSPI_IIO_AI_STM_MODE_CURRENT 0x1
#define NEURONSPI_IIO_AI_STM_MODE_RESISTANCE 0x3
/*********************
- * Board Definitions *
+ * Data Declarations *
*********************/
-// B_1000 (S103)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_B1000_HW_COMBINATION[];
-// E-8Di8Ro (M103)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION[];
-// E-14Ro
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E14RO_HW_COMBINATION[];
-// E-16Di
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DI_HW_COMBINATION[];
-// E-8Di8Ro_P-11DiR485 (xS10)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION[];
-// E-14Ro_P-11DiR485 (xS40)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION[];
-// E-16Di_P-11DiR485 (xS30)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION[];
-// E-14Ro_U-14Ro (M403)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION[];
-// E-16Di_U-14Ro (M203)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION[];
-// E-14Ro_U-14Di (L503)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION[];
-// E-16Di_U-14Di (M303)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION[];
-// E-4Ai4Ao
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION[];
-// E-4Ai4Ao_P-6Di5Ro (xS50)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION[];
-// B-485
-extern struct neuronspi_board_combination NEURONSPI_BOARD_B485_HW_COMBINATION[];
-// E-4Light (M613)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION[];
-// E-4Ai4Ao_U-6Di5Ro (L503)
-extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION[];
-
-/*********************
- * Model Definitions *
- *********************/
+extern struct platform_device *neuron_plc_dev;
+// Board Definitions
+extern struct neuronspi_board_combination NEURONSPI_BOARD_B1000_HW_COMBINATION[]; // B_1000 (S103)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION[]; // E-8Di8Ro (M103)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E14RO_HW_COMBINATION[]; // E-14Ro
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DI_HW_COMBINATION[]; // E-16Di
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION[]; // E-8Di8Ro_P-11DiR485 (xS10)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION[]; // E-14Ro_P-11DiR485 (xS40)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION[]; // E-16Di_P-11DiR485 (xS30)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION[]; // E-14Ro_U-14Ro (M403)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION[]; // E-16Di_U-14Ro (M203)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION[]; // E-14Ro_U-14Di (L503)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION[]; // E-16Di_U-14Di (M303)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION[]; // E-4Ai4Ao
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION[]; // E-4Ai4Ao_P-6Di5Ro (xS50)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_B485_HW_COMBINATION[]; // B-485
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION[]; // E-4Light (M613)
+extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION[]; // E-4Ai4Ao_U-6Di5Ro (L503)
+
+// Model Definitions
#define NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE 1
extern struct neuronspi_board_combination NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE];
#define NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD_SIZE 1
extern struct neuronspi_board_combination NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD[];
// Board table
-// Column 4 is the number of 0-indexed registers and column 5 is the number of 1000-indexed ones
#define NEURONSPI_BOARDTABLE_LEN 16
extern struct neuronspi_board_entry NEURONSPI_BOARDTABLE[];
#define NEURONSPI_MODELTABLE_LEN 15
extern struct neuronspi_model_definition NEURONSPI_MODELTABLE[];
-extern struct platform_device *neuron_plc_dev;
+/*************************
+ * Function Declarations *
+ *************************/
int neuronspi_regmap_hw_gather_write(void *context, const void *reg, size_t reg_size, const void *val, size_t val_size);
int neuronspi_regmap_hw_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf, size_t val_size);
int neuronspi_regmap_hw_reg_read(void *context, unsigned int reg, unsigned int *val);
int neuronspi_regmap_hw_reg_write(void *context, unsigned int reg, unsigned int val);
int neuronspi_regmap_hw_write(void *context, const void *data, size_t count);
-
void neuronspi_regmap_invalidate_device(struct regmap *reg_map, struct neuronspi_board_combination *device_def, u32 period_counter);
s32 neuronspi_regmap_invalidate(void *data);
int neuronspi_create_reg_starts(struct neuronspi_board_regstart_table *out_table, struct neuronspi_board_combination *board);
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+/************
+ * Includes *
+ ************/
+
#include "unipi_common.h"
#include "unipi_sysfs.h"
#include "unipi_uart.h"
#include "unipi_misc.h"
#include "unipi_spi.h"
+/********************
+ * Data Definitions *
+ ********************/
+
MODULE_DEVICE_TABLE(of, neuronspi_id_match);
struct spi_driver neuronspi_spi_driver =
struct spi_device* neuronspi_s_dev[NEURONSPI_MAX_DEVS];
struct task_struct *neuronspi_invalidate_thread;
-/***********************
- * End of Data section *
- ***********************/
+/************************
+ * Non-static Functions *
+ ************************/
int neuronspi_open (struct inode *inode_p, struct file *file_p)
{
if (d_data->slower_model) {
frequency = NEURONSPI_SLOWER_FREQ;
}
-
neuronspi_spi_compose_single_register_read(503, &message_buf, &recv_buf);
if (!d_data->reserved_device) {
neuronspi_spi_send_message(spi_dev, message_buf, recv_buf, NEURONSPI_SPI_UART_SET_CFLAG_MESSAGE_LEN, frequency, 35, 1);
u32 sec_ai_val_h = 0;
u32 sec_ai_val_m = 0;
u8 sec_ai_exp = 0;
-
regmap_read(n_spi->reg_map, n_spi->regstart_table->sec_ai_val_reg + (2 * ai_data->index), &sec_ai_val_h);
regmap_read(n_spi->reg_map, n_spi->regstart_table->sec_ai_val_reg + 1 + (2 * ai_data->index), &sec_ai_val_l);
sec_ai_val_m = ((((u32)sec_ai_val_h) << 25) | (((u32)sec_ai_val_l) << 9)) >> 16;
u32 stm_v_inp_ref = 0;
u32 stm_v_err = 0;
u32 stm_v_off = 0;
-
u64 stm_true_val = val;
u64 stm_true_ref = 0;
-
regmap_read(n_spi->reg_map, n_spi->regstart_table->vref_int, &stm_v_int_ref);
regmap_read(n_spi->reg_map, n_spi->regstart_table->vref_inp, &stm_v_inp_ref);
regmap_read(n_spi->reg_map, n_spi->regstart_table->stm_ao_vol_err, &stm_v_err);
regmap_read(n_spi->reg_map, n_spi->regstart_table->stm_ao_vol_off, &stm_v_off);
-
stm_true_ref = ((u64)stm_v_int_ref) * (99000 + stm_v_err) * 1000;
stm_v_inp_ref = stm_v_inp_ref * 10000;
stm_true_val = ((stm_true_val * 10000) - stm_v_off) * 4095;
stm_v_inp_ref = stm_true_ref;
do_div(stm_true_val, stm_v_inp_ref);
do_div(stm_true_val, 10000);
-
if (stm_true_val > 4095) stm_true_val = 4095;
-
regmap_write(n_spi->reg_map, n_spi->regstart_table->stm_ao_val_reg, (unsigned int) stm_true_val);
}
}
return ret;
}
-module_init(neuronspi_init);
+__attribute__((unused)) module_init(neuronspi_init);
static void __exit neuronspi_exit(void)
{
kfree(neuronspi_spi_w_spinlock);
printk(KERN_INFO "NEURONSPI: SPI Driver Unregistered\n");
}
-module_exit(neuronspi_exit);
+__attribute__((unused)) module_exit(neuronspi_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tomas Knot <knot@faster.cz>");
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_SPI_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_SPI_H_
-
-#define NEURONSPI_SCHED_REQUIRED 0 // Older kernels do not require sched/types to be specifically imported
-
-#define NEURONSPI_MAJOR_VERSIONSTRING "Development Beta Version 0.02:12:02:2018"
+/************
+ * Includes *
+ ************/
#include <linux/bitops.h>
#include <linux/clk.h>
#include "unipi_sysfs.h"
#include "unipi_iio.h"
+/********************
+ * Module Constants *
+ ********************/
+
#define NEURONSPI_SLOWER_MODELS_LEN 3
static const u16 NEURONSPI_SLOWER_MODELS[NEURONSPI_SLOWER_MODELS_LEN] = {
0xb10, 0xc10, 0xf10
3458, 1922, 514
};
-
-
-/********************
- * Module Constants *
- ********************/
-
static const struct of_device_id neuronspi_id_match[] = {
{.compatible = "unipi,neuron"},
{.compatible = NEURON_DEVICE_NAME},
{}
};
+/***************
+ * Definitions *
+ ***************/
#define NEURON_INT_RX_NOT_EMPTY 0x1
#define NEURON_INT_TX_FINISHED 0x2
#define MODBUS_MAX_WR_WRITE_REGISTERS 121
#define MODBUS_MAX_WR_READ_REGISTERS 125
-/*******************
- * Data structures *
- *******************/
-
-
-
-/*************
- * Functions *
- *************/
+/*************************
+ * Function Declarations *
+ *************************/
int neuronspi_open (struct inode *, struct file *);
int neuronspi_release (struct inode *, struct file *);
int neuronspi_spi_gpio_do_set(struct spi_device* spi_dev, u32 id, int value);
int neuronspi_spi_gpio_ro_set(struct spi_device* spi_dev, u32 id, int value);
int neuronspi_spi_gpio_di_get(struct spi_device* spi_dev, u32 id);
-
int neuronspi_spi_gpio_di_get(struct spi_device* spi_dev, u32 id);
/***********************
#define to_uart_port(p,e) ((container_of((p), struct uart_port, e)))
-/***********************
- * Inline Functions *
- ***********************/
+/*********************
+ * In-line Functions *
+ *********************/
static __always_inline u16 neuronspi_spi_crc(u8* inputstring, s32 length, u16 initval)
{
*
*/
+/************
+ * Includes *
+ ************/
+
#include "unipi_sysfs.h"
+/************************
+ * Static Functions *
+ ************************/
static ssize_t neuronspi_show_model(struct device *dev, struct device_attribute *attr, char *buf)
{
return count;
}
+/**********************************
+ * Function Structure Definitions *
+ **********************************/
static DEVICE_ATTR(model_name, 0440, neuronspi_show_model, NULL);
static DEVICE_ATTR(sys_eeprom_name, 0440, neuronspi_show_eeprom, NULL);
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_SYSFS_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_SYSFS_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
*
*/
+/************
+ * Includes *
+ ************/
#include "unipi_uart.h"
#include "unipi_spi.h"
+/********************
+ * Data Definitions *
+ ********************/
+
struct neuronspi_uart_data* neuronspi_uart_glob_data;
unsigned long neuronspi_lines;
struct uart_driver* neuronspi_uart;
+/************************
+ * Non-static Functions *
+ ************************/
+
void neuronspi_uart_tx_proc(struct kthread_work *ws)
{
struct neuronspi_port *port = to_neuronspi_port(ws, tx_work);
u32 neuronspi_uart_get_mctrl(struct uart_port *port)
{
- /* DCD and DSR are not wired and CTS/RTS is handled automatically
- * so just indicate DSR and CAR asserted
- */
#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_DEBUG "NEURONSPI: UART MCTRL Get\n");
#endif
return TIOCM_DSR | TIOCM_CAR;
}
-void neuronspi_uart_set_mctrl(struct uart_port *port, u32 mctrl)
-{
- /* Do Nothing */
-}
-
int neuronspi_uart_ioctl (struct uart_port *port, unsigned int ioctl_code, unsigned long ioctl_arg)
{
switch (ioctl_code) {
return;
}
-void neuronspi_uart_break_ctl(struct uart_port *port, int break_state)
-{
-
-}
-
void neuronspi_uart_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)
{
s32 baud;
neuronspi_uart_set_ldisc(port, termios);
}
}
-
baud = uart_get_baud_rate(port, termios, old, 2400, 115200);
uart_update_timeout(port, termios->c_cflag, baud);
}
return 0;
}
-// Initialise the module
-s32 neuronspi_uart_startup(struct uart_port *port)
-{
- struct neuronspi_port *n_port = to_neuronspi_port(port, port);
- struct spi_device *spi = neuronspi_s_dev[n_port->dev_index];
- struct neuronspi_driver_data *d_data = spi_get_drvdata(spi);
- neuronspi_spi_set_irqs(spi, 0x5);
- if (d_data->poll_thread != NULL) {
- wake_up_process(d_data->poll_thread);
- } else if (d_data->no_irq) {
- d_data->poll_thread = kthread_create(neuronspi_uart_poll, (void *)d_data, "UART_poll_thread");
- }
- neuronspi_uart_power(port, 1);
- // TODO: /* Reset FIFOs*/
-#if NEURONSPI_DETAILED_DEBUG > 0
- printk(KERN_DEBUG "NEURONSPI: UART Startup\n");
-#endif
- return 0;
-}
-void neuronspi_uart_shutdown(struct uart_port *port)
-{
- neuronspi_uart_power(port, 0);
-}
const char* neuronspi_uart_type(struct uart_port *port)
{
return i;
}
-void neuronspi_uart_power(struct uart_port *port, s32 on)
-{
- /* Do nothing */
-}
void neuronspi_uart_handle_rx(struct neuronspi_port *port, u32 rxlen, u32 iir)
{
neuronspi_uart_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
}
-void neuronspi_uart_null_void(struct uart_port *port)
-{
- /* Do nothing */
-}
-
s32 neuronspi_uart_probe(struct spi_device* dev, u8 device_index)
{
struct neuronspi_driver_data* driver_data = spi_get_drvdata(dev);
kfree(send_buf);
}
-
-void neuronspi_uart_stop_tx(struct uart_port *port)
-{
- // ToDo : create new opcode / coil?
-}
-
-void neuronspi_uart_stop_rx(struct uart_port *port)
-{
- // ToDo : create new opcode / coil?
-}
-
void neuronspi_uart_start_tx(struct uart_port *port)
{
struct neuronspi_port *n_port = to_neuronspi_port(port,port);
}
return 0;
}
+
+// Initialise the driver
+s32 neuronspi_uart_startup(struct uart_port *port)
+{
+ struct neuronspi_port *n_port = to_neuronspi_port(port, port);
+ struct spi_device *spi = neuronspi_s_dev[n_port->dev_index];
+ struct neuronspi_driver_data *d_data = spi_get_drvdata(spi);
+ neuronspi_spi_set_irqs(spi, 0x5);
+ if (d_data->poll_thread != NULL) {
+ wake_up_process(d_data->poll_thread);
+ } else if (d_data->no_irq) {
+ d_data->poll_thread = kthread_create(neuronspi_uart_poll, (void *)d_data, "UART_poll_thread");
+ }
+ neuronspi_uart_power(port, 1);
+ // TODO: /* Reset FIFOs*/
+#if NEURONSPI_DETAILED_DEBUG > 0
+ printk(KERN_DEBUG "NEURONSPI: UART Startup\n");
+#endif
+ return 0;
+}
+
+void neuronspi_uart_shutdown(struct uart_port *port)
+{
+ neuronspi_uart_power(port, 0);
+}
+
+/*******************
+ * Empty functions *
+ *******************/
+
+void neuronspi_uart_stop_tx(struct uart_port *port)
+{
+ /* Do Nothing */
+}
+
+void neuronspi_uart_stop_rx(struct uart_port *port)
+{
+ /* Do Nothing */
+}
+void neuronspi_uart_set_mctrl(struct uart_port *port, u32 mctrl)
+{
+ /* Do Nothing */
+}
+void neuronspi_uart_break_ctl(struct uart_port *port, int break_state)
+{
+ /* Do Nothing */
+}
+void neuronspi_uart_power(struct uart_port *port, s32 on)
+{
+ /* Do nothing */
+}
+void neuronspi_uart_null_void(struct uart_port *port)
+{
+ /* Do nothing */
+}
#ifndef MODULES_NEURON_SPI_SRC_UNIPI_UART_H_
#define MODULES_NEURON_SPI_SRC_UNIPI_UART_H_
+/************
+ * Includes *
+ ************/
+
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include "unipi_platform.h"
-extern struct neuronspi_uart_data* neuronspi_uart_glob_data;
-extern unsigned long neuronspi_lines;
-extern struct uart_driver* neuronspi_uart;
+
+/*************************
+ * Function Declarations *
+ *************************/
void neuronspi_uart_start_tx(struct uart_port *port);
void neuronspi_uart_stop_tx(struct uart_port *port);
void neuronspi_uart_handle_rx(struct neuronspi_port *port, u32 rxlen, u32 iir);
void neuronspi_uart_handle_irq(struct neuronspi_uart_data *uart_data, u32 portno);
+/*********************
+ * Data Declarations *
+ *********************/
+
+extern struct neuronspi_uart_data* neuronspi_uart_glob_data;
+extern unsigned long neuronspi_lines;
+extern struct uart_driver* neuronspi_uart;
+
static const struct uart_ops neuronspi_uart_ops =
{
.tx_empty = neuronspi_uart_tx_empty,
git.graph-it.com / graphit / unipi-kernel.git / commitdiff