struct neuronspi_driver_data *n_spi;
struct platform_device *plat = to_platform_device(dev);
n_spi = platform_get_drvdata(plat);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: Index %d\n", n_spi->neuron_index);
+#endif
spi = neuronspi_s_dev[n_spi->neuron_index];
if (n_spi && n_spi->combination_id != 0xFF && n_spi->reg_map && n_spi->regstart_table->uart_conf_reg) {
read_length = neuronspi_spi_compose_single_register_read(504, &inp_buf, &outp_buf);
struct neuronspi_driver_data *n_spi;
struct platform_device *plat = to_platform_device(dev);
n_spi = platform_get_drvdata(plat);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: Index %d\n", n_spi->neuron_index);
+#endif
spi = neuronspi_s_dev[n_spi->neuron_index];
err = kstrtouint(buf, 0, &val);
if (err < 0) goto err_end;
struct spi_device *spi = ai_data->parent;
struct neuronspi_driver_data *n_spi = spi_get_drvdata(spi);
regmap_read(n_spi->reg_map, n_spi->regstart_table->stm_ai_mode_reg + ai_data->index, &val);
-
ret = scnprintf(buf, 255, "%d\n", val);
return ret;
}
struct neuronspi_analog_data *ao_data = iio_priv(indio_dev);
struct spi_device *spi = ao_data->parent;
struct neuronspi_driver_data *n_spi = spi_get_drvdata(spi);
-
regmap_read(n_spi->reg_map, n_spi->regstart_table->stm_ao_mode_reg + ao_data->index, &val);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: Mode register %d set to %x", n_spi->regstart_table->stm_ao_mode_reg + ao_data->index, val);
+#endif
ret = scnprintf(buf, 255, "%d\n", val);
return ret;
}
err = kstrtouint(buf, 0, &val);
if (err < 0) goto err_end;
if (n_spi && n_spi->combination_id != -1 && n_spi->reg_map) {
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: Mode register %d set to %x", n_spi->regstart_table->stm_ao_mode_reg + ao_data->index, val);
+#endif
regmap_write(n_spi->reg_map, n_spi->regstart_table->stm_ao_mode_reg + ao_data->index, val);
}
err_end:
return 1;
}
case 0x5481: {
-//#if NEURONSPI_DETAILED_DEBUG > 0
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: IOCTL 0x5481\n");
-//#endif
+#endif
write_length = neuronspi_spi_compose_single_register_write(NEURONSPI_UART_TIMEOUT_REGISTER, &inp_buf, &outp_buf, (ioctl_arg * 1000000) / n_port->baud);
printk(KERN_INFO "NEURONSPI: val_upper: %x, val_lower: %x", inp_buf[10], inp_buf[11]);
neuronspi_spi_send_message(spi, inp_buf, outp_buf, write_length, n_spi->ideal_frequency, 25, 1, 0);
return 0;
}
case 0x5480: {
-//#if NEURONSPI_DETAILED_DEBUG > 0
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: IOCTL 0x5480\n");
-//#endif
+#endif
write_length = neuronspi_spi_compose_single_register_write(NEURONSPI_UART_TIMEOUT_REGISTER, &inp_buf, &outp_buf, ioctl_arg * 10);
printk(KERN_INFO "NEURONSPI: val_upper: %x, val_lower: %x", inp_buf[10], inp_buf[11]);
neuronspi_spi_send_message(spi, inp_buf, outp_buf, write_length, n_spi->ideal_frequency, 25, 1, 0);
printk(KERN_INFO "NEURONSPI: c_iflag termios:%d\n", termios->c_iflag);
#endif
}
-//#if NEURONSPI_DETAILED_DEBUG > 0
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_DEBUG "NEURONSPI: TERMIOS Set, p:%d, c_cflag:%x\n", port->line, termios->c_cflag);
-//#endif
+#endif
neuronspi_spi_uart_set_cflag(neuronspi_s_dev[n_port->dev_index], n_port->dev_port, termios->c_cflag);
if (old && termios && (old->c_iflag & PARMRK) != (termios->c_iflag & PARMRK)) {
neuronspi_uart_set_iflags(port, termios->c_iflag);
}
}
if (old && termios && old->c_line != termios->c_line) {
- printk(KERN_INFO "NEURONSPI: Line Discipline change\n");
if (termios->c_line == N_PROFIBUS_FDL) {
#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: Line Discipline change\n");
s32 i;
struct neuronspi_port *s = to_neuronspi_port(port,port);
struct neuronspi_driver_data *d_data = spi_get_drvdata(neuronspi_s_dev[s->dev_index]);
-//#if NEURONSPI_DETAILED_DEBUG > 2
+#if NEURONSPI_DETAILED_DEBUG > 2
printk(KERN_INFO "NEURONSPI: FIFO Read len:%d\n", rxlen);
-//#endif
+#endif
memcpy(s->buf, d_data->uart_buf, rxlen);
for (i = 0; i < rxlen; i++) {
-//#if NEURONSPI_DETAILED_DEBUG > 2
+#if NEURONSPI_DETAILED_DEBUG > 2
printk(KERN_INFO "NEURONSPI: UART Char Read: %x\n", d_data->uart_buf[i]);
-//#endif
+#endif
}
}
spin_lock_irqsave(&port->port.lock, flags);
to_send = uart_circ_chars_pending(xmit);
spin_unlock_irqrestore(&port->port.lock, flags);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI UART_HANDLE_TX A, to_send:%d\n", to_send);
+#endif
if (likely(to_send)) {
/* Limit to size of (TX FIFO / 2) */
max_txlen = NEURONSPI_FIFO_SIZE >> 2;
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
}
spin_unlock_irqrestore(&port->port.lock, flags);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI UART_HANDLE_TX B, to_send:%d\n", to_send_packet);
+#endif
neuronspi_uart_fifo_write(port, to_send_packet);
spin_lock_irqsave(&port->port.lock, flags);
to_send = uart_circ_chars_pending(xmit);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
}
spin_unlock_irqrestore(&port->port.lock, flags);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI UART_HANDLE_TX C, to_send:%d\n", to_send_packet);
+#endif
neuronspi_uart_fifo_write(port, to_send_packet);
}
kthread_init_work(&(uart_data->p[i].rx_work), neuronspi_uart_rx_proc);
kthread_init_work(&(uart_data->p[i].irq_work), neuronspi_uart_ist);
uart_add_one_port(driver_data->serial_driver, &uart_data->p[i].port);
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: Added UART port %d\n", i);
+#endif
}
// For ports on multiple SPI devices renumber the ports to correspond to SPI chip-select numbering
printk(KERN_INFO "NEURONSPI: Start TX\n");
#endif
if (!kthread_queue_work(&n_port->parent->kworker, &n_port->tx_work)) {
+#if NEURONSPI_DETAILED_DEBUG > 0
printk(KERN_INFO "NEURONSPI: TX WORK OVERFLOW\n");
+#endif
}
}