From 1791894bb70008c1f218d0a598012c9656a8fcd5 Mon Sep 17 00:00:00 2001 From: Tom Knot Date: Tue, 27 Feb 2018 14:34:48 +0100 Subject: [PATCH] Cleaned up issues with left-over static declarations --- modules/neuron_spi/bin/unipi.ko | Bin 97126 -> 96083 bytes modules/neuron_spi/src/unipi_common.h | 40 +- modules/neuron_spi/src/unipi_platform.c | 1459 ++++++++++++++++++++++ modules/neuron_spi/src/unipi_platform.h | 1469 +---------------------- modules/neuron_spi/src/unipi_spi.c | 37 +- modules/neuron_spi/src/unipi_spi.h | 99 +- modules/neuron_spi/src/unipi_sysfs.c | 287 ++++- modules/neuron_spi/src/unipi_sysfs.h | 240 +--- modules/neuron_spi/src/unipi_uart.c | 4 + modules/neuron_spi/src/unipi_uart.h | 5 + 10 files changed, 1837 insertions(+), 1803 deletions(-) diff --git a/modules/neuron_spi/bin/unipi.ko b/modules/neuron_spi/bin/unipi.ko index 62b75d5e8d71bf8cd4870a7cc9fe430fe8ace05d..62869f0908016e9371db462a88eca01e3d8b2678 100644 GIT binary patch literal 96083 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zU2U^-PuPfc@)evgX=+gW)iH)(#yGv<6MAGupE~zkMnh)rO`4&?OtCdfG)>9Q{ae~F7r4UdJZ~f1+)^#=LT}=-=|Cgx#r1^I8wop3 zhq)WpmuC;CF1y-&#zZ6C{5ZYLyqyYboXHWCGv05D#^CgRQ_9dcv&mR69e}x4$(T5% zOVlWFu9U9H>4w?)5?@4XNpiw<#Lmxc56yWPDo9Uz2k$h@h;$Ke2k3qvlDQ@;>~kYK zcKKakIB?_6Hs~<(CwA&~VwaxanQ4N*9O2s70W&67u<0SrCEM15m^Z-S2Gi7>%q)zS Iqw7QdKYCPA@&Et; diff --git a/modules/neuron_spi/src/unipi_common.h b/modules/neuron_spi/src/unipi_common.h index f8df483..eed7e08 100644 --- a/modules/neuron_spi/src/unipi_common.h +++ b/modules/neuron_spi/src/unipi_common.h @@ -67,7 +67,7 @@ #define NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(X) ((((X) + 15) >> 4) << 1) #define NEURONSPI_NO_INTERRUPT_MODELS_LEN 3 -static const uint16_t NEURONSPI_NO_INTERRUPT_MODELS[NEURONSPI_NO_INTERRUPT_MODELS_LEN] = { +static const u16 NEURONSPI_NO_INTERRUPT_MODELS[NEURONSPI_NO_INTERRUPT_MODELS_LEN] = { 0xb10, 0xc10, 0xf10 }; @@ -87,8 +87,8 @@ enum neuron_num_attribute_type { struct neuronspi_devtype { u8 name[10]; - int32_t nr_gpio; - int32_t nr_uart; + s32 nr_gpio; + s32 nr_uart; }; struct neuronspi_port @@ -121,7 +121,7 @@ struct neuronspi_uart_data // Instantiated once struct neuronspi_char_driver { - int32_t major_number; + s32 major_number; u8 *message; u16 message_size; u32 open_counter; @@ -168,10 +168,10 @@ struct neuronspi_driver_data u8 lower_board_id; u8 upper_board_id; u8 combination_id; - int32_t neuron_index; - uint16_t sysfs_regmap_target; - uint16_t sysfs_counter_target; - uint32_t ideal_frequency; + s32 neuron_index; + u16 sysfs_regmap_target; + u16 sysfs_counter_target; + u32 ideal_frequency; }; struct neuronspi_di_driver { @@ -250,7 +250,7 @@ struct neuronspi_led_driver spinlock_t lock; }; -static struct mutex neuronspi_master_mutex; +extern struct mutex neuronspi_master_mutex; struct neuronspi_file_data { @@ -258,7 +258,7 @@ struct neuronspi_file_data struct mutex lock; u8 *send_buf; u8 *recv_buf; - uint32_t message_len; + u32 message_len; }; struct neuronspi_direct_acc @@ -267,17 +267,13 @@ struct neuronspi_direct_acc u32 size; }; -static struct neuronspi_char_driver neuronspi_cdrv = -{ - .dev = NULL -}; - -static struct spinlock* neuronspi_spi_w_spinlock; -static u8 neuronspi_spi_w_flag = 1; -static u8 neuronspi_probe_count = 0; -static int neuronspi_model_id = -1; -static spinlock_t neuronspi_probe_spinlock; -static struct spi_device* neuronspi_s_dev[NEURONSPI_MAX_DEVS]; -static struct task_struct *neuronspi_invalidate_thread; +extern struct neuronspi_char_driver neuronspi_cdrv; +extern struct spinlock* neuronspi_spi_w_spinlock; +extern u8 neuronspi_spi_w_flag; +extern u8 neuronspi_probe_count; +extern int neuronspi_model_id; +extern spinlock_t neuronspi_probe_spinlock; +extern struct spi_device* neuronspi_s_dev[NEURONSPI_MAX_DEVS]; +extern struct task_struct *neuronspi_invalidate_thread; #endif /* MODULES_NEURON_SPI_SRC_UNIPI_COMMON_H_ */ diff --git a/modules/neuron_spi/src/unipi_platform.c b/modules/neuron_spi/src/unipi_platform.c index c2b0ec8..cda7fc7 100644 --- a/modules/neuron_spi/src/unipi_platform.c +++ b/modules/neuron_spi/src/unipi_platform.c @@ -9,6 +9,1465 @@ #include "unipi_spi.h" #include "unipi_common.h" +struct platform_device *neuron_plc_dev; + +/********************* + * Board Definitions * + *********************/ + +// B_1000 (S103) +#define NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE 57 +static u32 NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE] = { + 0, 21, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_AO_BRAIN | NEURONSPI_REGFLAG_ACC_AFAP, // 2 + NEURONSPI_REGFUN_AI_BRAIN | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 3 + NEURONSPI_REGFUN_AIO_BRAIN | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 4 + NEURONSPI_REGFUN_V_REF_INP | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 5 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 6 + NEURONSPI_REGFUN_TX_QUEUE_LEN | NEURONSPI_REGFLAG_ACC_10HZ, // 7 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 20 + 1000, 32, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1014 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1015 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1016 + NEURONSPI_REGFUN_PWM_PRESCALE | NEURONSPI_REGFLAG_ACC_1HZ, // 1017 + NEURONSPI_REGFUN_PWM_CYCLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 + NEURONSPI_REGFUN_AO_BRAIN_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 + NEURONSPI_REGFUN_AO_BRAIN_V_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1020 + NEURONSPI_REGFUN_AO_BRAIN_V_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1021 + NEURONSPI_REGFUN_AO_BRAIN_I_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1022 + NEURONSPI_REGFUN_AO_BRAIN_I_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1023 + NEURONSPI_REGFUN_AI_BRAIN_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1024 + NEURONSPI_REGFUN_AI_BRAIN_V_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1025 + NEURONSPI_REGFUN_AI_BRAIN_V_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1026 + NEURONSPI_REGFUN_AI_BRAIN_I_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1027 + NEURONSPI_REGFUN_AI_BRAIN_I_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1028 + NEURONSPI_REGFUN_AIO_BRAIN_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1029 + NEURONSPI_REGFUN_AIO_BRAIN_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1030 + NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC // 1031 +}; + +#define NEURONSPI_BOARD_B1000_HW_FEATURES { \ + .do_count = 4, \ + .ro_count = 0, \ + .ds_count = 4, \ + .di_count = 4, \ + .led_count = 4, \ + .stm_ai_count = 1, \ + .stm_ao_count = 1, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 1, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 4, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 1, \ +} + +#define NEURONSPI_BOARD_B1000_HW_DEFINITION { \ + .combination_board_id = 0, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_B1000_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .block_count = NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE, \ + .name_length = 6, \ + .combination_name = "B_1000", \ + .features = NEURONSPI_BOARD_B1000_HW_FEATURES, \ + .blocks = NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_B1000_HW_COMBINATION[] = {NEURONSPI_BOARD_B1000_HW_DEFINITION}; + +// E-8Di8Ro (M103) +#define NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK_SIZE 44 +static u32 NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 19, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + 1000, 17, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 +}; + +#define NEURONSPI_BOARD_E8DI8RO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 8, \ + .ds_count = 8, \ + .di_count = 8, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION { \ + .combination_board_id = 1, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .block_count = NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK_SIZE, \ + .name_length = 8, \ + .combination_name = "E_8Di8Ro", \ + .blocks = NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E8DI8RO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION}; + +// E-14Ro +#define NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK_SIZE 15 +static u32 NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 1, // Register block beginning and size + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 + 1000, 10, + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 +}; + +#define NEURONSPI_BOARD_E14RO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 14, \ + .ds_count = 0, \ + .di_count = 0, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E14RO_HW_DEFINITION { \ + .combination_board_id = 2, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .block_count = NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK_SIZE, \ + .name_length = 6, \ + .combination_name = "E_14Ro", \ + .blocks = NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E14RO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E14RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E14RO_HW_DEFINITION}; + +// E-16Di +#define NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK_SIZE 15 +static u32 NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK_SIZE] = { + 0, 1, // Register block beginning and size + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 + 1000, 10, + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 +}; + +#define NEURONSPI_BOARD_E16DI_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 0, \ + .ds_count = 0, \ + .di_count = 16, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E16DI_HW_DEFINITION { \ + .combination_board_id = 3, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .block_count = NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK_SIZE, \ + .name_length = 6, \ + .combination_name = "E_16Di", \ + .blocks = NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E16DI_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E16DI_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DI_HW_DEFINITION}; + +// E-8Di8Ro_P-11DiR485 (xS10) +#define NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK_SIZE 47 +static u32 NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK_SIZE] = { + 0, 20, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_1HZ, // 19 + 1000, 23, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 + NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 + NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1022 +}; + +#define NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 8, \ + .ds_count = 8, \ + .di_count = 8, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 1, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 1, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION { \ + .combination_board_id = 4, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, \ + .block_count = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK_SIZE, \ + .name_length = 19, \ + .combination_name = "E_8Di8Ro_P_11DiR485", \ + .blocks = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION[] = {NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION}; + +// E-14Ro_P-11DiR485 (xS40) +#define NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK_SIZE 71 +static u32 NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK_SIZE] = { + 0, 36, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 + NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_1HZ, // 35 + 1000, 31, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1026 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1027 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1028 + NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1029 + NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1030 +}; + +#define NEURONSPI_BOARD_E14ROP11DIR485_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 14, \ + .ds_count = 8, \ + .di_count = 8, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 1, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 1, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION { \ + .combination_board_id = 5, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, \ + .name_length = 17, \ + .combination_name = "E_14Ro_P_11DiR485", \ + .block_count = NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E14ROP11DIR485_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION[] = {NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION}; + +// E-16Di_P-11DiR485 (xS30) +#define NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK_SIZE 92 +static u32 NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK_SIZE] = { + 0, 52, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 35 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 36 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 37 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 38 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 39 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 40 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 41 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 42 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 43 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 44 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 45 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 46 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 47 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 48 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 49 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 50 + NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_1HZ, // 51 + 1000, 36, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1026 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1027 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1028 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1029 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1030 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1031 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1032 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1033 + NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1034 + NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1035 +}; + +#define NEURONSPI_BOARD_E16DIP11DIR485_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 0, \ + .ds_count = 0, \ + .di_count = 23, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 1, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 1, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION { \ + .combination_board_id = 6, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, \ + .name_length = 17, \ + .combination_name = "E_16Di_P_11DiR485", \ + .block_count = NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E16DIP11DIR485_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION}; + +// E-14Ro_U-14Ro (M403) +#define NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK_SIZE 17 +static u32 NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 3, // Register block beginning and size + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + 1000, 10, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 +}; + +#define NEURONSPI_BOARD_E14ROU14RO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 28, \ + .ds_count = 0, \ + .di_count = 0, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 1, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION { \ + .combination_board_id = 7, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, \ + .name_length = 13, \ + .combination_name = "E_14Ro_U_14Ro", \ + .block_count = NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E14ROU14RO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION}; + +// E-16Di_U-14Ro (M203) +#define NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK_SIZE 68 +static u32 NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 35, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 + 1000, 29, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1026 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1027 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1028 +}; + +#define NEURONSPI_BOARD_E16DIU14RO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 14, \ + .ds_count = 14, \ + .di_count = 16, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION { \ + .combination_board_id = 8, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, \ + .name_length = 13, \ + .combination_name = "E_16Di_U_14Ro", \ + .block_count = NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E16DIU14RO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION}; + +// E-14Ro_U-14Di (L503) +#define NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK_SIZE 62 +static u32 NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK_SIZE] = { + 0, 31, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 + 1000, 27, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1024 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1025 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ // 1026 +}; + +#define NEURONSPI_BOARD_E14ROU14DI_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 14, \ + .ds_count = 14, \ + .di_count = 14, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION { \ + .combination_board_id = 9, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, \ + .name_length = 13, \ + .combination_name = "E_14Ro_U_14Di", \ + .block_count = NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E14ROU14DI_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION[] = {NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION}; + + +// E-16Di_U-14Di (M303) +#define NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK_SIZE 107 +static u32 NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK_SIZE] = { + 0, 63, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 35 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 36 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 37 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 38 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 39 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 40 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 41 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 42 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 43 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 44 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 45 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 46 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 47 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 48 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 49 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 50 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 51 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 52 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 53 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 54 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 55 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 56 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 57 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 58 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 59 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 60 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 61 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 62 + 1000, 40, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1026 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1027 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1028 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1029 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1030 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1031 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1032 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1033 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1034 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1035 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1036 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1037 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1038 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1039 +}; + +#define NEURONSPI_BOARD_E16DIU14DI_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 0, \ + .ds_count = 0, \ + .di_count = 30, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION { \ + .combination_board_id = 10, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, \ + .name_length = 13, \ + .combination_name = "E_16Di_U_14Di", \ + .block_count = NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E16DIU14DI_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION}; + +// E-4Ai4Ao +#define NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK_SIZE 15 +static u32 NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 1, // Register block beginning and size + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + 1000, 10, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 +}; + +#define NEURONSPI_BOARD_E4AI4AO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 0, \ + .ds_count = 0, \ + .di_count = 0, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 4, \ + .sec_ao_count = 4, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + + +#define NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION { \ + .combination_board_id = 11, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .name_length = 8, \ + .combination_name = "E_4Ai4Ao", \ + .block_count = NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E4AI4AO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION}; + +// E-4Ai4Ao_P-6Di5Ro (xS50) +#define NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK_SIZE 56 +static u32 NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 27, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 2 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 3 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 4 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 5 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 6 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 7 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 8 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 9 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 10 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 11 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 12 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 13 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC, // 14 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + 1000, 25, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1016 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1017 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1021 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1022 + NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 + NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1024 +}; + +#define NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 6, \ + .ds_count = 5, \ + .di_count = 5, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 4, \ + .sec_ao_count = 4, \ + .uart_master_count = 0, \ + .uart_slave_count = 1, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 1, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION { \ + .combination_board_id = 12, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_P6DI5RO_ID, \ + .name_length = 17, \ + .combination_name = "E_4Ai4Ao_P_6Di5Ro", \ + .block_count = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION}; + +// B-485 +#define NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK_SIZE 15 +static u32 NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK_SIZE] = { + 0, 1, // Register block beginning and size + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 + 1000, 10, + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 +}; + +#define NEURONSPI_BOARD_B485_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 0, \ + .ds_count = 0, \ + .di_count = 0, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 4, \ + .sec_ao_count = 4, \ + .uart_master_count = 1, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 0, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_B485_HW_DEFINITION { \ + .combination_board_id = 13, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_B485_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .name_length = 5, \ + .combination_name = "B_485", \ + .block_count = NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_B485_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_B485_HW_COMBINATION[] = {NEURONSPI_BOARD_B485_HW_DEFINITION}; + +// E-4Light (M613) +#define NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK_SIZE 35 +static u32 NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK_SIZE] = { + 0, 21, // Register block beginning and size + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 1 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 2 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 3 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 4 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 5 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 6 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 7 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 8 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 9 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 10 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 11 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 12 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 13 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 14 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 15 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 16 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 17 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 18 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 19 + NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 20 + 1000, 10, + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 +}; + +#define NEURONSPI_BOARD_E4LIGHT_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 0, \ + .ds_count = 0, \ + .di_count = 0, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 0, \ + .sec_ao_count = 0, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 4, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION { \ + .combination_board_id = 14, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E4LIGHT_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ + .name_length = 8, \ + .combination_name = "E_4Light", \ + .block_count = NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E4LIGHT_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION[] = {NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION}; + +// E-4Ai4Ao_U-6Di5Ro (L503) +#define NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK_SIZE 56 +static u32 NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK_SIZE] = { + 0, 28, // Register block beginning and size + NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 + NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 2 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 3 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 4 + NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 5 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP, // 6 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP, // 7 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 8 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 9 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 10 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 11 + NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 12 + NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 13 + NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 14 + NEURONSPI_REGFUN_TX_QUEUE_LEN | NEURONSPI_REGFLAG_ACC_10HZ, // 15 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 + NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 + NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 + 1000, 24, // Register block beginning and size + NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 + NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 + NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 + NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 + NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 + NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1005 + NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1006 + NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 + NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 + NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 + NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 + NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1016 + NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1017 + NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1021 + NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1022 + NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC // 1023 +}; + +#define NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_FEATURES { \ + .do_count = 0, \ + .ro_count = 5, \ + .ds_count = 5, \ + .di_count = 6, \ + .led_count = 0, \ + .stm_ai_count = 0, \ + .stm_ao_count = 0, \ + .sec_ai_count = 4, \ + .sec_ao_count = 4, \ + .uart_master_count = 0, \ + .uart_slave_count = 0, \ + .pwm_channel_count = 0, \ + .wd_count = 1, \ + .extension_sys_count = 0, \ + .light_count = 4, \ + .owire_count = 0, \ +} + +#define NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION { \ + .combination_board_id = 15, \ + .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, \ + .upper_board_id = NEURONSPI_BOARD_UPPER_U6DI5RO_ID, \ + .name_length = 17, \ + .combination_name = "E_4Ai4Ao_U_6Di5Ro", \ + .block_count = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK_SIZE, \ + .blocks = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK, \ + .features = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_FEATURES \ +} +struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION}; + +/********************* + * Model Definitions * + *********************/ + +struct neuronspi_board_combination NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION +}; + +struct neuronspi_board_combination NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD_SIZE] = { + NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION +}; + +// Board table +// Column 4 is the number of 0-indexed registers and column 5 is the number of 1000-indexed ones +struct neuronspi_board_entry NEURONSPI_BOARDTABLE[NEURONSPI_BOARDTABLE_LEN] = { + {.index = 0, .lower_board_id = NEURONSPI_BOARD_LOWER_B1000_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 21, .config_register_count = 32, .definition = NEURONSPI_BOARD_B1000_HW_COMBINATION}, // B_1000 (S103) + {.index = 1, .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 19, .config_register_count = 21, .definition = NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION}, // E-8Di8Ro (M103) + {.index = 2, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_E14RO_HW_COMBINATION}, // E-14Ro + {.index = 3, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_E16DI_HW_COMBINATION}, // E-16Di + {.index = 4, .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, + .data_register_count = 36, .config_register_count = 31, .definition = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION}, // E-8Di8Ro_P-11DiR485 (xS10) + {.index = 5, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, + .data_register_count = 20, .config_register_count = 23, .definition = NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION}, // E-14Ro_P-11DiR485 (xS40) + {.index = 6, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, + .data_register_count = 52, .config_register_count = 36, .definition = NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION}, // E-16Di_P-11DiR485 (xS30) + {.index = 7, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, + .data_register_count = 3, .config_register_count = 10, .definition = NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION}, // E-14Ro_U-14Ro (M403) + {.index = 8, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, + .data_register_count = 35, .config_register_count = 29, .definition = NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION}, // E-16Di_U-14Ro (M203) + {.index = 9, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, + .data_register_count = 31, .config_register_count = 27, .definition = NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION}, // E-14Ro_U-14Di (L503) + {.index = 10, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, + .data_register_count = 63, .config_register_count = 40, .definition = NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION}, // E-16Di_U-14Di (M303) + {.index = 11, .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION}, // E-4Ai4Ao + {.index = 12, .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P6DI5RO_ID, + .data_register_count = 27, .config_register_count = 25, .definition = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION}, // E-4Ai4Ao_P-6Di5Ro (xS50) + {.index = 13, .lower_board_id = NEURONSPI_BOARD_LOWER_B485_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_B485_HW_COMBINATION}, // B-485 + {.index = 14, .lower_board_id = NEURONSPI_BOARD_LOWER_E4LIGHT_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, + .data_register_count = 21, .config_register_count = 8, .definition = NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION}, // E-4Light (M603) + {.index = 15, .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U6DI5RO_ID, + .data_register_count = 28, .config_register_count = 24, .definition = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION} // E-4Ai4Ao_U-6Di5Ro (M503) +}; + +// Module table +struct neuronspi_model_definition NEURONSPI_MODELTABLE[NEURONSPI_MODELTABLE_LEN] = { + {.eeprom_length = 4, .eeprom_name = "S103", .name_length = 4, .model_name = "S103", + .combination_count = 1, .combinations = NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "S103", .name_length = 6, .model_name = "S103-G", + .combination_count = 1, .combinations = NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD}, + {.eeprom_length = 6, .eeprom_name = "S103IQ", .name_length = 7, .model_name = "S103-IQ", + .combination_count = 1, .combinations = NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD}, + {.eeprom_length = 6, .eeprom_name = "S103EO", .name_length = 7, .model_name = "S103-EO", + .combination_count = 1, .combinations = NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "M103", .name_length = 4, .model_name = "M103", + .combination_count = 2, .combinations = NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "M203", .name_length = 4, .model_name = "M203", + .combination_count = 2, .combinations = NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "M303", .name_length = 4, .model_name = "M303", + .combination_count = 2, .combinations = NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "M403", .name_length = 4, .model_name = "M403", + .combination_count = 2, .combinations = NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "M503", .name_length = 4, .model_name = "M503", + .combination_count = 2, .combinations = NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "M603", .name_length = 4, .model_name = "M603", + .combination_count = 2, .combinations = NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "L203", .name_length = 4, .model_name = "L203", + .combination_count = 3, .combinations = NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "L303", .name_length = 4, .model_name = "L303", + .combination_count = 3, .combinations = NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "L403", .name_length = 4, .model_name = "L403", + .combination_count = 3, .combinations = NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "L503", .name_length = 4, .model_name = "L503", + .combination_count = 3, .combinations = NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD}, + {.eeprom_length = 4, .eeprom_name = "L513", .name_length = 4, .model_name = "L513", + .combination_count = 3, .combinations = NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD} +}; + s32 neuronspi_regmap_invalidate(void *data) { int i; diff --git a/modules/neuron_spi/src/unipi_platform.h b/modules/neuron_spi/src/unipi_platform.h index 6fd6aa1..4166a27 100644 --- a/modules/neuron_spi/src/unipi_platform.h +++ b/modules/neuron_spi/src/unipi_platform.h @@ -129,8 +129,8 @@ struct neuronspi_board_regstart_table struct neuronspi_board_combination { u32 combination_board_id; - uint16_t lower_board_id; - uint16_t upper_board_id; + u16 lower_board_id; + u16 upper_board_id; u32 block_count; size_t name_length; const char* combination_name; @@ -145,7 +145,7 @@ struct neuronspi_model_definition size_t name_length; const char* model_name; u32 combination_count; - struct neuronspi_board_combination *combinations; + struct neuronspi_board_combination *combinations; }; @@ -261,1476 +261,83 @@ struct neuronspi_model_definition *********************/ // B_1000 (S103) -#define NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE 57 -static u32 NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE] = { - 0, 21, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_AO_BRAIN | NEURONSPI_REGFLAG_ACC_AFAP, // 2 - NEURONSPI_REGFUN_AI_BRAIN | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 3 - NEURONSPI_REGFUN_AIO_BRAIN | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 4 - NEURONSPI_REGFUN_V_REF_INP | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 5 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 6 - NEURONSPI_REGFUN_TX_QUEUE_LEN | NEURONSPI_REGFLAG_ACC_10HZ, // 7 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_PWM_DUTY | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 20 - 1000, 32, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1014 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1015 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1016 - NEURONSPI_REGFUN_PWM_PRESCALE | NEURONSPI_REGFLAG_ACC_1HZ, // 1017 - NEURONSPI_REGFUN_PWM_CYCLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 - NEURONSPI_REGFUN_AO_BRAIN_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 - NEURONSPI_REGFUN_AO_BRAIN_V_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1020 - NEURONSPI_REGFUN_AO_BRAIN_V_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1021 - NEURONSPI_REGFUN_AO_BRAIN_I_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1022 - NEURONSPI_REGFUN_AO_BRAIN_I_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1023 - NEURONSPI_REGFUN_AI_BRAIN_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1024 - NEURONSPI_REGFUN_AI_BRAIN_V_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1025 - NEURONSPI_REGFUN_AI_BRAIN_V_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1026 - NEURONSPI_REGFUN_AI_BRAIN_I_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1027 - NEURONSPI_REGFUN_AI_BRAIN_I_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1028 - NEURONSPI_REGFUN_AIO_BRAIN_OFF | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1029 - NEURONSPI_REGFUN_AIO_BRAIN_ERR | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1030 - NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC // 1031 -}; - -#define NEURONSPI_BOARD_B1000_HW_FEATURES { \ - .do_count = 4, \ - .ro_count = 0, \ - .ds_count = 4, \ - .di_count = 4, \ - .led_count = 4, \ - .stm_ai_count = 1, \ - .stm_ao_count = 1, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 1, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 4, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 1, \ -} - -#define NEURONSPI_BOARD_B1000_HW_DEFINITION { \ - .combination_board_id = 0, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_B1000_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .block_count = NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK_SIZE, \ - .name_length = 6, \ - .combination_name = "B_1000", \ - .features = NEURONSPI_BOARD_B1000_HW_FEATURES, \ - .blocks = NEURONSPI_BOARD_B1000_HW_DEFINITION_BLOCK \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_B1000_HW_COMBINATION[] = {NEURONSPI_BOARD_B1000_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_B1000_HW_COMBINATION[]; // E-8Di8Ro (M103) -#define NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK_SIZE 44 -static u32 NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 19, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - 1000, 17, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 -}; - -#define NEURONSPI_BOARD_E8DI8RO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 8, \ - .ds_count = 8, \ - .di_count = 8, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION { \ - .combination_board_id = 1, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .block_count = NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK_SIZE, \ - .name_length = 8, \ - .combination_name = "E_8Di8Ro", \ - .blocks = NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E8DI8RO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION[]; // E-14Ro -#define NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK_SIZE 15 -static u32 NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 1, // Register block beginning and size - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 - 1000, 10, - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 -}; - -#define NEURONSPI_BOARD_E14RO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 14, \ - .ds_count = 0, \ - .di_count = 0, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E14RO_HW_DEFINITION { \ - .combination_board_id = 2, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .block_count = NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK_SIZE, \ - .name_length = 6, \ - .combination_name = "E_14Ro", \ - .blocks = NEURONSPI_BOARD_E14RO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E14RO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E14RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E14RO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E14RO_HW_COMBINATION[]; // E-16Di -#define NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK_SIZE 15 -static u32 NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK_SIZE] = { - 0, 1, // Register block beginning and size - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 - 1000, 10, - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 -}; - -#define NEURONSPI_BOARD_E16DI_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 0, \ - .ds_count = 0, \ - .di_count = 16, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E16DI_HW_DEFINITION { \ - .combination_board_id = 3, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .block_count = NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK_SIZE, \ - .name_length = 6, \ - .combination_name = "E_16Di", \ - .blocks = NEURONSPI_BOARD_E16DI_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E16DI_HW_FEATURES \ -} - -static struct neuronspi_board_combination NEURONSPI_BOARD_E16DI_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DI_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DI_HW_COMBINATION[]; // E-8Di8Ro_P-11DiR485 (xS10) -#define NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK_SIZE 47 -static u32 NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK_SIZE] = { - 0, 20, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_1HZ, // 19 - 1000, 23, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 - NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 - NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1022 -}; - -#define NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 8, \ - .ds_count = 8, \ - .di_count = 8, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 1, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 1, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION { \ - .combination_board_id = 4, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, \ - .block_count = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK_SIZE, \ - .name_length = 19, \ - .combination_name = "E_8Di8Ro_P_11DiR485", \ - .blocks = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION[] = {NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION[]; // E-14Ro_P-11DiR485 (xS40) -#define NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK_SIZE 71 -static u32 NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK_SIZE] = { - 0, 36, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 - NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_1HZ, // 35 - 1000, 31, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE, // 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE, // 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1026 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1027 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1028 - NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1029 - NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1030 -}; - -#define NEURONSPI_BOARD_E14ROP11DIR485_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 14, \ - .ds_count = 8, \ - .di_count = 8, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 1, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 1, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION { \ - .combination_board_id = 5, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, \ - .name_length = 17, \ - .combination_name = "E_14Ro_P_11DiR485", \ - .block_count = NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E14ROP11DIR485_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION[] = {NEURONSPI_BOARD_E14ROP11DIR485_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION[]; // E-16Di_P-11DiR485 (xS30) -#define NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK_SIZE 92 -static u32 NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK_SIZE] = { - 0, 52, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 35 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 36 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 37 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 38 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 39 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 40 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 41 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 42 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 43 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 44 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 45 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 46 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 47 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 48 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 49 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 50 - NEURONSPI_REGFUN_LED_RW | NEURONSPI_REGFLAG_ACC_1HZ, // 51 - 1000, 36, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1026 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1027 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1028 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1029 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1030 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1031 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1032 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1033 - NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1034 - NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1035 -}; - -#define NEURONSPI_BOARD_E16DIP11DIR485_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 0, \ - .ds_count = 0, \ - .di_count = 23, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 1, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 1, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION { \ - .combination_board_id = 6, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, \ - .name_length = 17, \ - .combination_name = "E_16Di_P_11DiR485", \ - .block_count = NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E16DIP11DIR485_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DIP11DIR485_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION[]; // E-14Ro_U-14Ro (M403) -#define NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK_SIZE 17 -static u32 NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 3, // Register block beginning and size - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - 1000, 10, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 -}; - -#define NEURONSPI_BOARD_E14ROU14RO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 28, \ - .ds_count = 0, \ - .di_count = 0, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 1, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION { \ - .combination_board_id = 7, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, \ - .name_length = 13, \ - .combination_name = "E_14Ro_U_14Ro", \ - .block_count = NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E14ROU14RO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION[]; // E-16Di_U-14Ro (M203) -#define NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK_SIZE 68 -static u32 NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 35, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 - 1000, 29, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1026 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1027 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1028 -}; - -#define NEURONSPI_BOARD_E16DIU14RO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 14, \ - .ds_count = 14, \ - .di_count = 16, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION { \ - .combination_board_id = 8, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, \ - .name_length = 13, \ - .combination_name = "E_16Di_U_14Ro", \ - .block_count = NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E16DIU14RO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION[]; // E-14Ro_U-14Di (L503) -#define NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK_SIZE 62 -static u32 NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK_SIZE] = { - 0, 31, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 - 1000, 27, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1024 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1025 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ // 1026 -}; - -#define NEURONSPI_BOARD_E14ROU14DI_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 14, \ - .ds_count = 14, \ - .di_count = 14, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION { \ - .combination_board_id = 9, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, \ - .name_length = 13, \ - .combination_name = "E_14Ro_U_14Di", \ - .block_count = NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E14ROU14DI_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION[] = {NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION}; - - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION[]; // E-16Di_U-14Di (M303) -#define NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK_SIZE 107 -static u32 NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK_SIZE] = { - 0, 63, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 2 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 3 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 4 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 5 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 6 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 7 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 8 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 9 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 10 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 11 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 12 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 13 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 28 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 29 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 30 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 31 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 32 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 33 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 34 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 35 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 36 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 37 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 38 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 39 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 40 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 41 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 42 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 43 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 44 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 45 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 46 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 47 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 48 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 49 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 50 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 51 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 52 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 53 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 54 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 55 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 56 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 57 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 58 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 59 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 60 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 61 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 62 - 1000, 40, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1016 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1017 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1018 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1019 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1020 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1021 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1022 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1024 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1025 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1026 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1027 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1028 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1029 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1030 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1031 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1032 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1033 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1034 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1035 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1036 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1037 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1038 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1039 -}; - -#define NEURONSPI_BOARD_E16DIU14DI_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 0, \ - .ds_count = 0, \ - .di_count = 30, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION { \ - .combination_board_id = 10, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, \ - .name_length = 13, \ - .combination_name = "E_16Di_U_14Di", \ - .block_count = NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E16DIU14DI_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION[] = {NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION[]; // E-4Ai4Ao -#define NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK_SIZE 15 -static u32 NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 1, // Register block beginning and size - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - 1000, 10, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 -}; - -#define NEURONSPI_BOARD_E4AI4AO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 0, \ - .ds_count = 0, \ - .di_count = 0, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 4, \ - .sec_ao_count = 4, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - - -#define NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION { \ - .combination_board_id = 11, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .name_length = 8, \ - .combination_name = "E_4Ai4Ao", \ - .block_count = NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E4AI4AO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION[]; // E-4Ai4Ao_P-6Di5Ro (xS50) -#define NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK_SIZE 56 -static u32 NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 27, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 2 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 3 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 4 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 5 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 6 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 7 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 8 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 9 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 10 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 11 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 12 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 13 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC, // 14 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 15 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - 1000, 25, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1016 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1017 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1021 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1022 - NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC, // 1023 - NEURONSPI_REGFUN_RS485_ADDRESS | NEURONSPI_REGFLAG_ACC_6SEC // 1024 -}; - -#define NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 6, \ - .ds_count = 5, \ - .di_count = 5, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 4, \ - .sec_ao_count = 4, \ - .uart_master_count = 0, \ - .uart_slave_count = 1, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 1, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION { \ - .combination_board_id = 12, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_P6DI5RO_ID, \ - .name_length = 17, \ - .combination_name = "E_4Ai4Ao_P_6Di5Ro", \ - .block_count = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION[]; // B-485 -#define NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK_SIZE 15 -static u32 NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK_SIZE] = { - 0, 1, // Register block beginning and size - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 - 1000, 10, - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 -}; - -#define NEURONSPI_BOARD_B485_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 0, \ - .ds_count = 0, \ - .di_count = 0, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 4, \ - .sec_ao_count = 4, \ - .uart_master_count = 1, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 0, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_B485_HW_DEFINITION { \ - .combination_board_id = 13, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_B485_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .name_length = 5, \ - .combination_name = "B_485", \ - .block_count = NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_B485_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_B485_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_B485_HW_COMBINATION[] = {NEURONSPI_BOARD_B485_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_B485_HW_COMBINATION[]; // E-4Light (M613) -#define NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK_SIZE 35 -static u32 NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK_SIZE] = { - 0, 21, // Register block beginning and size - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 0 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 1 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 2 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 3 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 4 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 5 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 6 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 7 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 8 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 9 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 10 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 11 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 12 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 13 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 14 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 15 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 16 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 17 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 18 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 19 - NEURONSPI_REGFUN_NONE_TEST | NEURONSPI_REGFLAG_ACC_ONCE, // 20 - 1000, 10, - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY,// 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 -}; - -#define NEURONSPI_BOARD_E4LIGHT_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 0, \ - .ds_count = 0, \ - .di_count = 0, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 0, \ - .sec_ao_count = 0, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 4, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION { \ - .combination_board_id = 14, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E4LIGHT_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, \ - .name_length = 8, \ - .combination_name = "E_4Light", \ - .block_count = NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E4LIGHT_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION[] = {NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION[]; // E-4Ai4Ao_U-6Di5Ro (L503) -#define NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK_SIZE 56 -static u32 NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK[NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK_SIZE] = { - 0, 28, // Register block beginning and size - NEURONSPI_REGFUN_DI_READ | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 0 - NEURONSPI_REGFUN_DO_RW | NEURONSPI_REGFLAG_ACC_10HZ, // 1 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 2 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 3 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 4 - NEURONSPI_REGFUN_AO_VER2_RW | NEURONSPI_REGFLAG_ACC_AFAP, // 5 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP, // 6 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP, // 7 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 8 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 9 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 10 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 11 - NEURONSPI_REGFUN_AI_VER2_READ_LOWER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 12 - NEURONSPI_REGFUN_AI_VER2_READ_UPPER | NEURONSPI_REGFLAG_ACC_AFAP | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 13 - NEURONSPI_REGFUN_MWD_STATUS | NEURONSPI_REGFLAG_ACC_6SEC | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 14 - NEURONSPI_REGFUN_TX_QUEUE_LEN | NEURONSPI_REGFLAG_ACC_10HZ, // 15 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 16 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 17 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 18 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 19 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 20 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 21 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 22 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 23 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 24 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 25 - NEURONSPI_REGFUN_DI_COUNTER_LOWER | NEURONSPI_REGFLAG_ACC_6SEC, // 26 - NEURONSPI_REGFUN_DI_COUNTER_UPPER | NEURONSPI_REGFLAG_ACC_6SEC, // 27 - 1000, 24, // Register block beginning and size - NEURONSPI_REGFUN_SW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1000 - NEURONSPI_REGFUN_DIDO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1001 - NEURONSPI_REGFUN_UAIO_COUNT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1002 - NEURONSPI_REGFUN_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1003 - NEURONSPI_REGFUN_FLASH_HW_VER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1004 - NEURONSPI_REGFUN_SERIAL_NR_LOWER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1005 - NEURONSPI_REGFUN_SERIAL_NR_UPPER | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1006 - NEURONSPI_REGFUN_INTERRUPTS | NEURONSPI_REGFLAG_ACC_AFAP, // 1007 - NEURONSPI_REGFUN_MWD_TO | NEURONSPI_REGFLAG_ACC_6SEC, // 1008 - NEURONSPI_REGFUN_V_REF_INT | NEURONSPI_REGFLAG_ACC_ONCE | NEURONSPI_REGFLAG_SYS_READ_ONLY, // 1009 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1010 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1011 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1012 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1013 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1014 - NEURONSPI_REGFUN_DI_DEBOUNCE | NEURONSPI_REGFLAG_ACC_6SEC, // 1015 - NEURONSPI_REGFUN_DS_ENABLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1016 - NEURONSPI_REGFUN_DS_POLARITY | NEURONSPI_REGFLAG_ACC_1HZ, // 1017 - NEURONSPI_REGFUN_DS_TOGGLE | NEURONSPI_REGFLAG_ACC_1HZ, // 1018 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1019 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1020 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1021 - NEURONSPI_REGFUN_AI_VER2_MODE | NEURONSPI_REGFLAG_ACC_1HZ, // 1022 - NEURONSPI_REGFUN_RS485_CONFIG | NEURONSPI_REGFLAG_ACC_6SEC // 1023 -}; - -#define NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_FEATURES { \ - .do_count = 0, \ - .ro_count = 5, \ - .ds_count = 5, \ - .di_count = 6, \ - .led_count = 0, \ - .stm_ai_count = 0, \ - .stm_ao_count = 0, \ - .sec_ai_count = 4, \ - .sec_ao_count = 4, \ - .uart_master_count = 0, \ - .uart_slave_count = 0, \ - .pwm_channel_count = 0, \ - .wd_count = 1, \ - .extension_sys_count = 0, \ - .light_count = 4, \ - .owire_count = 0, \ -} - -#define NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION { \ - .combination_board_id = 15, \ - .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, \ - .upper_board_id = NEURONSPI_BOARD_UPPER_U6DI5RO_ID, \ - .name_length = 17, \ - .combination_name = "E_4Ai4Ao_U_6Di5Ro", \ - .block_count = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK_SIZE, \ - .blocks = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION_BLOCK, \ - .features = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_FEATURES \ -} -static struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION[] = {NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION}; - +extern struct neuronspi_board_combination NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION[]; /********************* * Model Definitions * *********************/ #define NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE 1 -static struct neuronspi_board_combination NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD_SIZE 1 -static struct neuronspi_board_combination NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD_SIZE 1 -static struct neuronspi_board_combination NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD_SIZE 1 -static struct neuronspi_board_combination NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD[NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD_SIZE 2 -static struct neuronspi_board_combination NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E8DI8RO_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD_SIZE 2 -static struct neuronspi_board_combination NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD_SIZE 2 -static struct neuronspi_board_combination NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD_SIZE 2 -static struct neuronspi_board_combination NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD_SIZE 2 -static struct neuronspi_board_combination NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD_SIZE 2 -static struct neuronspi_board_combination NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4LIGHT_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD[NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD_SIZE 3 -static struct neuronspi_board_combination NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14RO_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD_SIZE 3 -static struct neuronspi_board_combination NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION, NEURONSPI_BOARD_E16DIU14DI_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD_SIZE 3 -static struct neuronspi_board_combination NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14RO_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD_SIZE 3 -static struct neuronspi_board_combination NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION, NEURONSPI_BOARD_E14ROU14DI_HW_DEFINITION -}; - +extern struct neuronspi_board_combination NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD_SIZE]; #define NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD_SIZE 3 -static struct neuronspi_board_combination NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD[NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD_SIZE] = { - NEURONSPI_BOARD_B1000_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION, NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_DEFINITION -}; +extern struct neuronspi_board_combination NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD[]; // Board table // Column 4 is the number of 0-indexed registers and column 5 is the number of 1000-indexed ones #define NEURONSPI_BOARDTABLE_LEN 16 -static struct neuronspi_board_entry NEURONSPI_BOARDTABLE[NEURONSPI_BOARDTABLE_LEN] = { - {.index = 0, .lower_board_id = NEURONSPI_BOARD_LOWER_B1000_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 21, .config_register_count = 32, .definition = NEURONSPI_BOARD_B1000_HW_COMBINATION}, // B_1000 (S103) - {.index = 1, .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 19, .config_register_count = 21, .definition = NEURONSPI_BOARD_E8DI8RO_HW_COMBINATION}, // E-8Di8Ro (M103) - {.index = 2, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_E14RO_HW_COMBINATION}, // E-14Ro - {.index = 3, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_E16DI_HW_COMBINATION}, // E-16Di - {.index = 4, .lower_board_id = NEURONSPI_BOARD_LOWER_E8DI8RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, - .data_register_count = 36, .config_register_count = 31, .definition = NEURONSPI_BOARD_E8DI8ROP11DIR485_HW_COMBINATION}, // E-8Di8Ro_P-11DiR485 (xS10) - {.index = 5, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, - .data_register_count = 20, .config_register_count = 23, .definition = NEURONSPI_BOARD_E14ROP11DIR485_HW_COMBINATION}, // E-14Ro_P-11DiR485 (xS40) - {.index = 6, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P11DIR485_ID, - .data_register_count = 52, .config_register_count = 36, .definition = NEURONSPI_BOARD_E16DIP11DIR485_HW_COMBINATION}, // E-16Di_P-11DiR485 (xS30) - {.index = 7, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, - .data_register_count = 3, .config_register_count = 10, .definition = NEURONSPI_BOARD_E14ROU14RO_HW_COMBINATION}, // E-14Ro_U-14Ro (M403) - {.index = 8, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14RO_ID, - .data_register_count = 35, .config_register_count = 29, .definition = NEURONSPI_BOARD_E16DIU14RO_HW_COMBINATION}, // E-16Di_U-14Ro (M203) - {.index = 9, .lower_board_id = NEURONSPI_BOARD_LOWER_E14RO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, - .data_register_count = 31, .config_register_count = 27, .definition = NEURONSPI_BOARD_E14ROU14DI_HW_COMBINATION}, // E-14Ro_U-14Di (L503) - {.index = 10, .lower_board_id = NEURONSPI_BOARD_LOWER_E16DI_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U14DI_ID, - .data_register_count = 63, .config_register_count = 40, .definition = NEURONSPI_BOARD_E16DIU14DI_HW_COMBINATION}, // E-16Di_U-14Di (M303) - {.index = 11, .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_E4AI4AO_HW_COMBINATION}, // E-4Ai4Ao - {.index = 12, .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_P6DI5RO_ID, - .data_register_count = 27, .config_register_count = 25, .definition = NEURONSPI_BOARD_E4AI4AOP6DI5RO_HW_COMBINATION}, // E-4Ai4Ao_P-6Di5Ro (xS50) - {.index = 13, .lower_board_id = NEURONSPI_BOARD_LOWER_B485_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 1, .config_register_count = 0, .definition = NEURONSPI_BOARD_B485_HW_COMBINATION}, // B-485 - {.index = 14, .lower_board_id = NEURONSPI_BOARD_LOWER_E4LIGHT_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_NONE_ID, - .data_register_count = 21, .config_register_count = 8, .definition = NEURONSPI_BOARD_E4LIGHT_HW_COMBINATION}, // E-4Light (M603) - {.index = 15, .lower_board_id = NEURONSPI_BOARD_LOWER_E4AI4AO_ID, .upper_board_id = NEURONSPI_BOARD_UPPER_U6DI5RO_ID, - .data_register_count = 28, .config_register_count = 24, .definition = NEURONSPI_BOARD_E4AI4AOU6DI5RO_HW_COMBINATION} // E-4Ai4Ao_U-6Di5Ro (M503) -}; +extern struct neuronspi_board_entry NEURONSPI_BOARDTABLE[]; // Module table #define NEURONSPI_MODELTABLE_LEN 15 -static struct neuronspi_model_definition NEURONSPI_MODELTABLE[NEURONSPI_MODELTABLE_LEN] = { - {.eeprom_length = 4, .eeprom_name = "S103", .name_length = 4, .model_name = "S103", - .combination_count = 1, .combinations = NEURONSPI_MODEL_S103_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "S103", .name_length = 6, .model_name = "S103-G", - .combination_count = 1, .combinations = NEURONSPI_MODEL_S103G_HW_DEFINITION_BOARD}, - {.eeprom_length = 6, .eeprom_name = "S103IQ", .name_length = 7, .model_name = "S103-IQ", - .combination_count = 1, .combinations = NEURONSPI_MODEL_S103IQ_HW_DEFINITION_BOARD}, - {.eeprom_length = 6, .eeprom_name = "S103EO", .name_length = 7, .model_name = "S103-EO", - .combination_count = 1, .combinations = NEURONSPI_MODEL_S103EO_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "M103", .name_length = 4, .model_name = "M103", - .combination_count = 2, .combinations = NEURONSPI_MODEL_M103_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "M203", .name_length = 4, .model_name = "M203", - .combination_count = 2, .combinations = NEURONSPI_MODEL_M203_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "M303", .name_length = 4, .model_name = "M303", - .combination_count = 2, .combinations = NEURONSPI_MODEL_M303_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "M403", .name_length = 4, .model_name = "M403", - .combination_count = 2, .combinations = NEURONSPI_MODEL_M403_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "M503", .name_length = 4, .model_name = "M503", - .combination_count = 2, .combinations = NEURONSPI_MODEL_M503_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "M603", .name_length = 4, .model_name = "M603", - .combination_count = 2, .combinations = NEURONSPI_MODEL_M603_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "L203", .name_length = 4, .model_name = "L203", - .combination_count = 3, .combinations = NEURONSPI_MODEL_L203_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "L303", .name_length = 4, .model_name = "L303", - .combination_count = 3, .combinations = NEURONSPI_MODEL_L303_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "L403", .name_length = 4, .model_name = "L403", - .combination_count = 3, .combinations = NEURONSPI_MODEL_L403_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "L503", .name_length = 4, .model_name = "L503", - .combination_count = 3, .combinations = NEURONSPI_MODEL_L503_HW_DEFINITION_BOARD}, - {.eeprom_length = 4, .eeprom_name = "L513", .name_length = 4, .model_name = "L513", - .combination_count = 3, .combinations = NEURONSPI_MODEL_L513_HW_DEFINITION_BOARD} -}; +extern struct neuronspi_model_definition NEURONSPI_MODELTABLE[]; + +extern struct platform_device *neuron_plc_dev; int neuronspi_regmap_hw_gather_write(void *context, const void *reg, size_t reg_size, const void *val, size_t val_size); int neuronspi_regmap_hw_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf, size_t val_size); diff --git a/modules/neuron_spi/src/unipi_spi.c b/modules/neuron_spi/src/unipi_spi.c index 544fa6b..ae6401f 100644 --- a/modules/neuron_spi/src/unipi_spi.c +++ b/modules/neuron_spi/src/unipi_spi.c @@ -13,6 +13,8 @@ nologies * */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include "unipi_common.h" #include "unipi_sysfs.h" #include "unipi_uart.h" @@ -22,9 +24,42 @@ nologies #include "unipi_misc.h" #include "unipi_spi.h" -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt MODULE_DEVICE_TABLE(of, neuronspi_id_match); +struct spi_driver neuronspi_spi_driver = +{ + .driver = + { + .name = NEURON_DRIVER_NAME, + .of_match_table = of_match_ptr(neuronspi_id_match) + }, + .probe = neuronspi_spi_probe, + .remove = neuronspi_spi_remove, +}; + +struct file_operations file_ops = +{ + .open = neuronspi_open, + .read = neuronspi_read, + .write = neuronspi_write, + .release = neuronspi_release, + .owner = THIS_MODULE +}; + +struct neuronspi_char_driver neuronspi_cdrv = +{ + .dev = NULL +}; + +struct mutex neuronspi_master_mutex; +struct spinlock* neuronspi_spi_w_spinlock; +u8 neuronspi_spi_w_flag = 1; +u8 neuronspi_probe_count = 0; +int neuronspi_model_id = -1; +spinlock_t neuronspi_probe_spinlock; +struct spi_device* neuronspi_s_dev[NEURONSPI_MAX_DEVS]; +struct task_struct *neuronspi_invalidate_thread; + /*********************** * End of Data section * ***********************/ diff --git a/modules/neuron_spi/src/unipi_spi.h b/modules/neuron_spi/src/unipi_spi.h index 3f73461..b38f97d 100644 --- a/modules/neuron_spi/src/unipi_spi.h +++ b/modules/neuron_spi/src/unipi_spi.h @@ -50,7 +50,7 @@ #include "unipi_iio.h" #define NEURONSPI_SLOWER_MODELS_LEN 3 -static const uint16_t NEURONSPI_SLOWER_MODELS[NEURONSPI_SLOWER_MODELS_LEN] = { +static const u16 NEURONSPI_SLOWER_MODELS[NEURONSPI_SLOWER_MODELS_LEN] = { 0xb10, 0xc10, 0xf10 }; @@ -119,7 +119,7 @@ static const u8 NEURONSPI_SPI_LED_SET_MESSAGE[NEURONSPI_SPI_LED_SET_MESSAGE_LEN] }; #define NEURONSPI_CRC16TABLE_LEN 256 -static const uint16_t NEURONSPI_CRC16TABLE[NEURONSPI_CRC16TABLE_LEN] = { +static const u16 NEURONSPI_CRC16TABLE[NEURONSPI_CRC16TABLE_LEN] = { 0, 1408, 3968, 2560, 7040, 7680, 5120, 4480, 13184, 13824, 15360, 14720, 10240, 11648, 10112, 8704, 25472, 26112, 27648, 27008, 30720, 32128, 30592, 29184, 20480, 21888, 24448, 23040, 19328, 19968, 17408, 16768, 50048, @@ -184,11 +184,6 @@ static const struct of_device_id neuronspi_id_match[] = { *******************/ -static struct neuronspi_uart_data* neuronspi_uart_glob_data; - -static unsigned long neuronspi_lines; - -static struct uart_driver* neuronspi_uart; /************* * Functions * @@ -198,17 +193,15 @@ int neuronspi_open (struct inode *, struct file *); int neuronspi_release (struct inode *, struct file *); ssize_t neuronspi_read (struct file *, char *, size_t, loff_t *); ssize_t neuronspi_write (struct file *, const char *, size_t, loff_t *); -int32_t char_register_driver(void); -int32_t char_unregister_driver(void); - -irqreturn_t neuronspi_spi_irq(int32_t irq, void *dev_id); -static int32_t neuronspi_spi_probe(struct spi_device *spi); -static int32_t neuronspi_spi_remove(struct spi_device *spi); -void neuronspi_spi_send_message(struct spi_device *spi_dev, u8 *send_buf, u8 *recv_buf, int32_t len, int32_t freq, int32_t delay, int32_t send_header); -//uint16_t neuronspi_spi_crc(u8* inputstring, int32_t length, uint16_t initval); -int32_t neuronspi_spi_uart_write(struct spi_device *spi, u8 *send_buf, u8 length, u8 uart_index); -void neuronspi_spi_uart_read(struct spi_device* spi_dev, u8 *send_buf, u8 *recv_buf, int32_t len, u8 uart_index); -void neuronspi_spi_set_irqs(struct spi_device* spi_dev, uint16_t to); +s32 char_register_driver(void); +s32 char_unregister_driver(void); +irqreturn_t neuronspi_spi_irq(s32 irq, void *dev_id); +s32 neuronspi_spi_probe(struct spi_device *spi); +s32 neuronspi_spi_remove(struct spi_device *spi); +void neuronspi_spi_send_message(struct spi_device *spi_dev, u8 *send_buf, u8 *recv_buf, s32 len, s32 freq, s32 delay, s32 send_header); +s32 neuronspi_spi_uart_write(struct spi_device *spi, u8 *send_buf, u8 length, u8 uart_index); +void neuronspi_spi_uart_read(struct spi_device* spi_dev, u8 *send_buf, u8 *recv_buf, s32 len, u8 uart_index); +void neuronspi_spi_set_irqs(struct spi_device* spi_dev, u16 to); void neuronspi_spi_led_set_brightness(struct spi_device* spi_dev, enum led_brightness brightness, int id); void neuronspi_spi_iio_stm_ai_read_voltage(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask); void neuronspi_spi_iio_stm_ai_read_current(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask); @@ -219,37 +212,19 @@ void neuronspi_spi_iio_sec_ai_read_voltage(struct iio_dev *iio_dev, struct iio_c void neuronspi_spi_iio_sec_ai_read_current(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask); void neuronspi_spi_iio_sec_ai_read_resistance(struct iio_dev *iio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask); void neuronspi_spi_iio_sec_ao_set_voltage(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask); -int neuronspi_spi_gpio_do_set(struct spi_device* spi_dev, uint32_t id, int value); -int neuronspi_spi_gpio_ro_set(struct spi_device* spi_dev, uint32_t id, int value); -int neuronspi_spi_gpio_di_get(struct spi_device* spi_dev, uint32_t id); +int neuronspi_spi_gpio_do_set(struct spi_device* spi_dev, u32 id, int value); +int neuronspi_spi_gpio_ro_set(struct spi_device* spi_dev, u32 id, int value); +int neuronspi_spi_gpio_di_get(struct spi_device* spi_dev, u32 id); -int neuronspi_spi_gpio_di_get(struct spi_device* spi_dev, uint32_t id); +int neuronspi_spi_gpio_di_get(struct spi_device* spi_dev, u32 id); /*********************** * Function structures * ***********************/ // Host driver struct -static struct spi_driver neuronspi_spi_driver = -{ - .driver = - { - .name = NEURON_DRIVER_NAME, - .of_match_table = of_match_ptr(neuronspi_id_match) - }, - .probe = neuronspi_spi_probe, - .remove = neuronspi_spi_remove, -}; - -static struct file_operations file_ops = -{ - .open = neuronspi_open, - .read = neuronspi_read, - .write = neuronspi_write, - .release = neuronspi_release, - .owner = THIS_MODULE -}; - +extern struct spi_driver neuronspi_spi_driver; +extern struct file_operations file_ops; static const struct regmap_bus neuronspi_regmap_bus = { @@ -353,8 +328,6 @@ static const struct iio_chan_spec neuronspi_sec_ao_chan_spec[] = { } }; -static struct platform_device *neuron_plc_dev; - static const struct iio_info neuronspi_stm_ai_info = { .read_raw = neuronspi_iio_stm_ai_read_raw, .driver_module = THIS_MODULE, @@ -391,19 +364,19 @@ static const struct iio_info neuronspi_sec_ao_info = { * Inline Functions * ***********************/ -static __always_inline uint16_t neuronspi_spi_crc(u8* inputstring, int32_t length, uint16_t initval) +static __always_inline u16 neuronspi_spi_crc(u8* inputstring, s32 length, u16 initval) { - int32_t i; - uint16_t result = initval; + s32 i; + u16 result = initval; for (i=0; i> 8) ^ NEURONSPI_CRC16TABLE[(result ^ inputstring[i]) & 0xff]; } return result; } -static __always_inline size_t neuronspi_spi_compose_single_coil_write(uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp, uint8_t data) +static __always_inline size_t neuronspi_spi_compose_single_coil_write(u16 start, u8 **buf_inp, u8 **buf_outp, u8 data) { - uint16_t crc1; + u16 crc1; *buf_outp = kzalloc(6, GFP_KERNEL); *buf_inp = kzalloc(6, GFP_KERNEL); (*buf_inp)[0] = 0x05; @@ -415,9 +388,9 @@ static __always_inline size_t neuronspi_spi_compose_single_coil_write(uint16_t s return 6; } -static __always_inline size_t neuronspi_spi_compose_single_coil_read(uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp) +static __always_inline size_t neuronspi_spi_compose_single_coil_read(u16 start, u8 **buf_inp, u8 **buf_outp) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(14, GFP_KERNEL); *buf_inp = kzalloc(14, GFP_KERNEL); (*buf_inp)[0] = 0x01; @@ -432,9 +405,9 @@ static __always_inline size_t neuronspi_spi_compose_single_coil_read(uint16_t st return 14; } -static __always_inline size_t neuronspi_spi_compose_multiple_coil_write(uint8_t number, uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp, uint8_t *data) +static __always_inline size_t neuronspi_spi_compose_multiple_coil_write(u8 number, u16 start, u8 **buf_inp, u8 **buf_outp, u8 *data) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(12 + NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(number), GFP_KERNEL); *buf_inp = kzalloc(12 + NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(number), GFP_KERNEL); (*buf_inp)[0] = 0x0F; @@ -451,9 +424,9 @@ static __always_inline size_t neuronspi_spi_compose_multiple_coil_write(uint8_t return 12 + NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(number); } -static __always_inline size_t neuronspi_spi_compose_multiple_coil_read(uint8_t number, uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp) +static __always_inline size_t neuronspi_spi_compose_multiple_coil_read(u8 number, u16 start, u8 **buf_inp, u8 **buf_outp) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(12 + NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(number), GFP_KERNEL); *buf_inp = kzalloc(12 + NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(number), GFP_KERNEL); (*buf_inp)[0] = 0x01; @@ -468,9 +441,9 @@ static __always_inline size_t neuronspi_spi_compose_multiple_coil_read(uint8_t n return 12 + NEURONSPI_GET_COIL_READ_PHASE2_BYTE_LENGTH(number); } -static __always_inline size_t neuronspi_spi_compose_single_register_write(uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp, uint16_t data) +static __always_inline size_t neuronspi_spi_compose_single_register_write(u16 start, u8 **buf_inp, u8 **buf_outp, u16 data) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(14, GFP_KERNEL); *buf_inp = kzalloc(14, GFP_KERNEL); (*buf_inp)[0] = 0x06; @@ -488,9 +461,9 @@ static __always_inline size_t neuronspi_spi_compose_single_register_write(uint16 return 14; } -static __always_inline size_t neuronspi_spi_compose_single_register_read(uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp) +static __always_inline size_t neuronspi_spi_compose_single_register_read(u16 start, u8 **buf_inp, u8 **buf_outp) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(14, GFP_KERNEL); *buf_inp = kzalloc(14, GFP_KERNEL); (*buf_inp)[0] = 0x03; @@ -506,9 +479,9 @@ static __always_inline size_t neuronspi_spi_compose_single_register_read(uint16_ return 14; } -static __always_inline size_t neuronspi_spi_compose_multiple_register_write(uint8_t number, uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp, uint8_t *data) +static __always_inline size_t neuronspi_spi_compose_multiple_register_write(u8 number, u16 start, u8 **buf_inp, u8 **buf_outp, u8 *data) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(12 + (number * 2), GFP_KERNEL); *buf_inp = kzalloc(12 + (number * 2), GFP_KERNEL); (*buf_inp)[0] = 0x10; @@ -525,9 +498,9 @@ static __always_inline size_t neuronspi_spi_compose_multiple_register_write(uint return 12 + (number * 2); } -static __always_inline size_t neuronspi_spi_compose_multiple_register_read(uint8_t number, uint16_t start, uint8_t **buf_inp, uint8_t **buf_outp) +static __always_inline size_t neuronspi_spi_compose_multiple_register_read(u8 number, u16 start, u8 **buf_inp, u8 **buf_outp) { - uint16_t crc1, crc2; + u16 crc1, crc2; *buf_outp = kzalloc(12 + (number * 2), GFP_KERNEL); *buf_inp = kzalloc(12 + (number * 2), GFP_KERNEL); (*buf_inp)[0] = 0x03; diff --git a/modules/neuron_spi/src/unipi_sysfs.c b/modules/neuron_spi/src/unipi_sysfs.c index 35ccafc..9449b3f 100644 --- a/modules/neuron_spi/src/unipi_sysfs.c +++ b/modules/neuron_spi/src/unipi_sysfs.c @@ -15,7 +15,7 @@ #include "unipi_sysfs.h" -ssize_t neuronspi_show_model(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_show_model(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; if (neuronspi_model_id != -1) { @@ -24,7 +24,7 @@ ssize_t neuronspi_show_model(struct device *dev, struct device_attribute *attr, return ret; } -ssize_t neuronspi_show_eeprom(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_show_eeprom(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; if (neuronspi_model_id != -1) { @@ -33,7 +33,7 @@ ssize_t neuronspi_show_eeprom(struct device *dev, struct device_attribute *attr, return ret; } -ssize_t neuronspi_spi_show_serial(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_serial(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val[2] = {0, 0}; @@ -48,7 +48,7 @@ ssize_t neuronspi_spi_show_serial(struct device *dev, struct device_attribute *a return ret; } -ssize_t neuronspi_spi_show_hw_version(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_hw_version(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -62,7 +62,7 @@ ssize_t neuronspi_spi_show_hw_version(struct device *dev, struct device_attribut return ret; } -ssize_t neuronspi_spi_show_hw_flash_version(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_hw_flash_version(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -76,7 +76,7 @@ ssize_t neuronspi_spi_show_hw_flash_version(struct device *dev, struct device_at return ret; } -ssize_t neuronspi_spi_show_fw_version(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_fw_version(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -90,7 +90,7 @@ ssize_t neuronspi_spi_show_fw_version(struct device *dev, struct device_attribut return ret; } -ssize_t neuronspi_spi_show_uart_queue_length(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_uart_queue_length(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -104,7 +104,7 @@ ssize_t neuronspi_spi_show_uart_queue_length(struct device *dev, struct device_a return ret; } -ssize_t neuronspi_spi_show_uart_config(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_uart_config(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -118,7 +118,7 @@ ssize_t neuronspi_spi_show_uart_config(struct device *dev, struct device_attribu return ret; } -ssize_t neuronspi_spi_store_uart_config(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_store_uart_config(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -134,7 +134,7 @@ err_end: return count; } -ssize_t neuronspi_spi_show_watchdog_status(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_watchdog_status(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -148,7 +148,7 @@ ssize_t neuronspi_spi_show_watchdog_status(struct device *dev, struct device_att return ret; } -ssize_t neuronspi_spi_store_watchdog_status(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_store_watchdog_status(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -164,7 +164,7 @@ err_end: return count; } -ssize_t neuronspi_spi_show_watchdog_timeout(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_watchdog_timeout(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -178,7 +178,7 @@ ssize_t neuronspi_spi_show_watchdog_timeout(struct device *dev, struct device_at return ret; } -ssize_t neuronspi_spi_store_watchdog_timeout(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_store_watchdog_timeout(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -194,7 +194,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_show_pwm_presc(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_pwm_presc(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -210,7 +210,7 @@ ssize_t neuronspi_spi_gpio_show_pwm_presc(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_store_pwm_presc(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_store_pwm_presc(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -228,7 +228,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_show_pwm_freq(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_pwm_freq(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -244,7 +244,7 @@ ssize_t neuronspi_spi_gpio_show_pwm_freq(struct device *dev, struct device_attri return ret; } -ssize_t neuronspi_spi_gpio_store_pwm_freq(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_store_pwm_freq(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -262,7 +262,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_show_pwm_cycle(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_pwm_cycle(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -278,7 +278,7 @@ ssize_t neuronspi_spi_gpio_show_pwm_cycle(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_store_pwm_cycle(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_store_pwm_cycle(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -296,7 +296,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_di_show_counter(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_di_show_counter(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -312,7 +312,7 @@ ssize_t neuronspi_spi_gpio_di_show_counter(struct device *dev, struct device_att return ret; } -ssize_t neuronspi_spi_gpio_di_store_counter(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_di_store_counter(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -330,7 +330,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_di_show_debounce(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_di_show_debounce(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -346,7 +346,7 @@ ssize_t neuronspi_spi_gpio_di_show_debounce(struct device *dev, struct device_at return ret; } -ssize_t neuronspi_spi_gpio_di_store_debounce(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_di_store_debounce(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -364,7 +364,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_di_show_value(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_di_show_value(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; int val; @@ -382,7 +382,7 @@ ssize_t neuronspi_spi_gpio_di_show_value(struct device *dev, struct device_attri return ret; } -ssize_t neuronspi_spi_gpio_do_show_value(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_do_show_value(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; int val; @@ -400,7 +400,7 @@ ssize_t neuronspi_spi_gpio_do_show_value(struct device *dev, struct device_attri return ret; } -ssize_t neuronspi_spi_gpio_do_store_value(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_do_store_value(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; int inp = 0; @@ -425,7 +425,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_ro_show_value(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_ro_show_value(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; int val; @@ -443,7 +443,7 @@ ssize_t neuronspi_spi_gpio_ro_show_value(struct device *dev, struct device_attri return ret; } -ssize_t neuronspi_spi_gpio_ro_store_value(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_ro_store_value(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; int inp = 0; @@ -469,7 +469,7 @@ err_end: } -ssize_t neuronspi_spi_gpio_show_ds_enable(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_ds_enable(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; int val; @@ -487,7 +487,7 @@ ssize_t neuronspi_spi_gpio_show_ds_enable(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_show_ds_toggle(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_ds_toggle(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; int val; @@ -505,7 +505,7 @@ ssize_t neuronspi_spi_gpio_show_ds_toggle(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_show_ds_polarity(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_ds_polarity(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; int val; @@ -523,7 +523,7 @@ ssize_t neuronspi_spi_gpio_show_ds_polarity(struct device *dev, struct device_at return ret; } -ssize_t neuronspi_spi_gpio_store_ds_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_store_ds_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; int inp = 0; @@ -548,7 +548,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_store_ds_toggle(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_store_ds_toggle(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; int inp = 0; @@ -573,7 +573,7 @@ err_end: return count; } -ssize_t neuronspi_spi_gpio_store_ds_polarity(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_spi_gpio_store_ds_polarity(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; int inp = 0; @@ -598,7 +598,7 @@ err_end: return count; } -ssize_t neuronspi_show_regmap(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_show_regmap(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; u32 val = 0; @@ -614,7 +614,7 @@ ssize_t neuronspi_show_regmap(struct device *dev, struct device_attribute *attr, return ret; } -ssize_t neuronspi_store_regmap(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_store_regmap(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -632,7 +632,7 @@ err_end: return count; } -ssize_t neuronspi_spi_show_board(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_board(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_driver_data *n_spi; @@ -644,7 +644,7 @@ ssize_t neuronspi_spi_show_board(struct device *dev, struct device_attribute *at return ret; } -ssize_t neuronspi_spi_show_lboard_id(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_lboard_id(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_driver_data *n_spi; @@ -656,7 +656,7 @@ ssize_t neuronspi_spi_show_lboard_id(struct device *dev, struct device_attribute return ret; } -ssize_t neuronspi_spi_show_uboard_id(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_show_uboard_id(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_driver_data *n_spi; @@ -668,7 +668,7 @@ ssize_t neuronspi_spi_show_uboard_id(struct device *dev, struct device_attribute return ret; } -ssize_t neuronspi_spi_gpio_show_do_prefix(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_do_prefix(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_do_driver *n_do; @@ -682,7 +682,7 @@ ssize_t neuronspi_spi_gpio_show_do_prefix(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_show_di_prefix(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_di_prefix(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_di_driver *n_di; @@ -696,7 +696,7 @@ ssize_t neuronspi_spi_gpio_show_di_prefix(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_show_ro_prefix(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_ro_prefix(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_ro_driver *n_ro; @@ -710,7 +710,7 @@ ssize_t neuronspi_spi_gpio_show_ro_prefix(struct device *dev, struct device_attr return ret; } -ssize_t neuronspi_spi_gpio_show_do_base(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_do_base(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_do_driver *n_do; @@ -724,7 +724,7 @@ ssize_t neuronspi_spi_gpio_show_do_base(struct device *dev, struct device_attrib return ret; } -ssize_t neuronspi_spi_gpio_show_di_base(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_di_base(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_di_driver *n_di; @@ -738,7 +738,7 @@ ssize_t neuronspi_spi_gpio_show_di_base(struct device *dev, struct device_attrib return ret; } -ssize_t neuronspi_spi_gpio_show_ro_base(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_ro_base(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_ro_driver *n_ro; @@ -752,7 +752,7 @@ ssize_t neuronspi_spi_gpio_show_ro_base(struct device *dev, struct device_attrib return ret; } -ssize_t neuronspi_spi_gpio_show_do_count(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_do_count(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_do_driver *n_do; @@ -766,7 +766,7 @@ ssize_t neuronspi_spi_gpio_show_do_count(struct device *dev, struct device_attri return ret; } -ssize_t neuronspi_spi_gpio_show_di_count(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_di_count(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_di_driver *n_di; @@ -780,7 +780,7 @@ ssize_t neuronspi_spi_gpio_show_di_count(struct device *dev, struct device_attri return ret; } -ssize_t neuronspi_spi_gpio_show_ro_count(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_spi_gpio_show_ro_count(struct device *dev, struct device_attribute *attr, char *buf) { ssize_t ret = 0; struct neuronspi_ro_driver *n_ro; @@ -795,7 +795,7 @@ ssize_t neuronspi_spi_gpio_show_ro_count(struct device *dev, struct device_attri } -ssize_t neuronspi_iio_show_primary_ai_mode(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_iio_show_primary_ai_mode(struct device *dev, struct device_attribute *attr, char *buf) { int ret = 0; unsigned int val = 0; @@ -808,7 +808,7 @@ ssize_t neuronspi_iio_show_primary_ai_mode(struct device *dev, struct device_att return ret; } -ssize_t neuronspi_iio_store_primary_ai_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_iio_store_primary_ai_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -825,7 +825,7 @@ err_end: return count; } -ssize_t neuronspi_iio_show_primary_ao_mode(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_iio_show_primary_ao_mode(struct device *dev, struct device_attribute *attr, char *buf) { int ret = 0; unsigned int val = 0; @@ -838,7 +838,7 @@ ssize_t neuronspi_iio_show_primary_ao_mode(struct device *dev, struct device_att return ret; } -ssize_t neuronspi_iio_store_primary_ao_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_iio_store_primary_ao_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -855,7 +855,7 @@ err_end: return count; } -ssize_t neuronspi_iio_show_secondary_ai_mode(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_iio_show_secondary_ai_mode(struct device *dev, struct device_attribute *attr, char *buf) { int ret = 0; unsigned int val = 0; @@ -867,7 +867,7 @@ ssize_t neuronspi_iio_show_secondary_ai_mode(struct device *dev, struct device_a ret = scnprintf(buf, 255, "%d\n", val); return ret; } -ssize_t neuronspi_iio_store_secondary_ai_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_iio_store_secondary_ai_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -883,7 +883,7 @@ ssize_t neuronspi_iio_store_secondary_ai_mode(struct device *dev, struct device_ err_end: return count; } -ssize_t neuronspi_iio_show_secondary_ao_mode(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t neuronspi_iio_show_secondary_ao_mode(struct device *dev, struct device_attribute *attr, char *buf) { int ret = 0; unsigned int val = 0; @@ -895,7 +895,7 @@ ssize_t neuronspi_iio_show_secondary_ao_mode(struct device *dev, struct device_a ret = scnprintf(buf, 255, "%d\n", val); return ret; } -ssize_t neuronspi_iio_store_secondary_ao_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t neuronspi_iio_store_secondary_ao_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { ssize_t err = 0; unsigned int val = 0; @@ -911,3 +911,178 @@ ssize_t neuronspi_iio_store_secondary_ao_mode(struct device *dev, struct device_ err_end: return count; } + + +static DEVICE_ATTR(model_name, 0440, neuronspi_show_model, NULL); +static DEVICE_ATTR(sys_eeprom_name, 0440, neuronspi_show_eeprom, NULL); +static DEVICE_ATTR(register_read, 0660, neuronspi_show_regmap, neuronspi_store_regmap); +static DEVICE_ATTR(sys_board_serial, 0440, neuronspi_spi_show_serial, NULL); +static DEVICE_ATTR(sys_board_name, 0440, neuronspi_spi_show_board, NULL); +static DEVICE_ATTR(sys_primary_major_id, 0440, neuronspi_spi_show_lboard_id, NULL); +static DEVICE_ATTR(sys_secondary_major_id, 0440, neuronspi_spi_show_uboard_id, NULL); +static DEVICE_ATTR(sys_primary_minor_id, 0440, neuronspi_spi_show_hw_version, NULL); +static DEVICE_ATTR(sys_secondary_minor_id, 0440, neuronspi_spi_show_hw_flash_version, NULL); +static DEVICE_ATTR(firmware_version, 0440, neuronspi_spi_show_fw_version, NULL); +static DEVICE_ATTR(watchdog_status, 0660, neuronspi_spi_show_watchdog_status, neuronspi_spi_store_watchdog_status); +static DEVICE_ATTR(watchdog_timeout, 0660, neuronspi_spi_show_watchdog_timeout, neuronspi_spi_store_watchdog_timeout); +static DEVICE_ATTR(sys_gpio_do_count, 0440, neuronspi_spi_gpio_show_do_count, NULL); +static DEVICE_ATTR(sys_gpio_do_prefix, 0440, neuronspi_spi_gpio_show_do_prefix, NULL); +static DEVICE_ATTR(sys_gpio_do_base, 0440, neuronspi_spi_gpio_show_do_base, NULL); +static DEVICE_ATTR(sys_gpio_di_count, 0440, neuronspi_spi_gpio_show_di_count, NULL); +static DEVICE_ATTR(sys_gpio_di_prefix, 0440, neuronspi_spi_gpio_show_di_prefix, NULL); +static DEVICE_ATTR(ro_value, 0660, neuronspi_spi_gpio_ro_show_value, neuronspi_spi_gpio_ro_store_value); +static DEVICE_ATTR(do_value, 0660, neuronspi_spi_gpio_do_show_value, neuronspi_spi_gpio_do_store_value); +static DEVICE_ATTR(counter, 0660, neuronspi_spi_gpio_di_show_counter, neuronspi_spi_gpio_di_store_counter); +static DEVICE_ATTR(debounce, 0660, neuronspi_spi_gpio_di_show_debounce, neuronspi_spi_gpio_di_store_debounce); +static DEVICE_ATTR(di_value, 0440, neuronspi_spi_gpio_di_show_value, NULL); +static DEVICE_ATTR(direct_switch_enable, 0660, neuronspi_spi_gpio_show_ds_enable, neuronspi_spi_gpio_store_ds_enable); +static DEVICE_ATTR(direct_switch_toggle, 0660, neuronspi_spi_gpio_show_ds_toggle, neuronspi_spi_gpio_store_ds_toggle); +static DEVICE_ATTR(direct_switch_polarity, 0660, neuronspi_spi_gpio_show_ds_polarity, neuronspi_spi_gpio_store_ds_polarity); +static DEVICE_ATTR(pwm_frequency_cycle, 0660, neuronspi_spi_gpio_show_pwm_freq, neuronspi_spi_gpio_store_pwm_freq); +static DEVICE_ATTR(pwm_prescale, 0660, neuronspi_spi_gpio_show_pwm_presc, neuronspi_spi_gpio_store_pwm_presc); +static DEVICE_ATTR(pwm_duty_cycle, 0660, neuronspi_spi_gpio_show_pwm_cycle, neuronspi_spi_gpio_store_pwm_cycle); +static DEVICE_ATTR(uart_queue_length, 0440, neuronspi_spi_show_uart_queue_length, NULL); +static DEVICE_ATTR(uart_config, 0660, neuronspi_spi_show_uart_config, neuronspi_spi_store_uart_config); +static DEVICE_ATTR(sys_gpio_di_base, 0440, neuronspi_spi_gpio_show_di_base, NULL); +static DEVICE_ATTR(sys_gpio_ro_count, 0440, neuronspi_spi_gpio_show_ro_count, NULL); +static DEVICE_ATTR(sys_gpio_ro_prefix, 0440, neuronspi_spi_gpio_show_ro_prefix, NULL); +static DEVICE_ATTR(sys_gpio_ro_base, 0440, neuronspi_spi_gpio_show_ro_base, NULL); +static DEVICE_ATTR(mode_ai_type_a, 0660, neuronspi_iio_show_primary_ai_mode, neuronspi_iio_store_primary_ai_mode); +static DEVICE_ATTR(mode_ao_type_a, 0660, neuronspi_iio_show_primary_ao_mode, neuronspi_iio_store_primary_ao_mode); +static DEVICE_ATTR(mode_ai_type_b, 0660, neuronspi_iio_show_secondary_ai_mode, neuronspi_iio_store_secondary_ai_mode); +static DEVICE_ATTR(mode_ao_type_b, 0660, neuronspi_iio_show_secondary_ao_mode, neuronspi_iio_store_secondary_ao_mode); + +static struct attribute *neuron_plc_attrs[] = { + &dev_attr_model_name.attr, + &dev_attr_sys_eeprom_name.attr, + NULL, +}; + +static struct attribute *neuron_board_attrs[] = { + &dev_attr_sys_board_name.attr, + &dev_attr_sys_primary_major_id.attr, + &dev_attr_sys_secondary_major_id.attr, + &dev_attr_sys_primary_minor_id.attr, + &dev_attr_sys_secondary_minor_id.attr, + &dev_attr_firmware_version.attr, + &dev_attr_watchdog_status.attr, + &dev_attr_watchdog_timeout.attr, + &dev_attr_sys_board_serial.attr, + &dev_attr_uart_queue_length.attr, + &dev_attr_uart_config.attr, + &dev_attr_register_read.attr, + NULL, +}; + +static struct attribute *neuron_gpio_di_attrs[] = { + &dev_attr_sys_gpio_di_count.attr, + &dev_attr_sys_gpio_di_prefix.attr, + &dev_attr_sys_gpio_di_base.attr, + &dev_attr_direct_switch_enable.attr, + &dev_attr_direct_switch_toggle.attr, + &dev_attr_direct_switch_polarity.attr, + &dev_attr_di_value.attr, + &dev_attr_counter.attr, + &dev_attr_debounce.attr, + NULL, +}; + +static struct attribute *neuron_gpio_do_attrs[] = { + &dev_attr_sys_gpio_do_count.attr, + &dev_attr_sys_gpio_do_prefix.attr, + &dev_attr_sys_gpio_do_base.attr, + &dev_attr_pwm_frequency_cycle.attr, + &dev_attr_pwm_prescale.attr, + &dev_attr_pwm_duty_cycle.attr, + &dev_attr_do_value.attr, + NULL, +}; + +static struct attribute *neuron_gpio_ro_attrs[] = { + &dev_attr_sys_gpio_ro_count.attr, + &dev_attr_sys_gpio_ro_prefix.attr, + &dev_attr_sys_gpio_ro_base.attr, + &dev_attr_ro_value.attr, + NULL, +}; + +static struct attribute *neuron_stm_ai_attrs[] = { + &dev_attr_mode_ai_type_a.attr, + NULL, +}; + +static struct attribute *neuron_stm_ao_attrs[] = { + &dev_attr_mode_ao_type_a.attr, + NULL, +}; + +static struct attribute *neuron_sec_ai_attrs[] = { + &dev_attr_mode_ai_type_b.attr, + NULL, +}; + +static struct attribute *neuron_sec_ao_attrs[] = { + &dev_attr_mode_ao_type_b.attr, + NULL, +}; + +static struct attribute_group neuron_plc_attr_group = { + .attrs = neuron_plc_attrs, +}; + +static struct attribute_group neuron_board_attr_group = { + .attrs = neuron_board_attrs, +}; + +static struct attribute_group neuron_gpio_di_attr_group = { + .attrs = neuron_gpio_di_attrs, +}; + +static struct attribute_group neuron_gpio_do_attr_group = { + .attrs = neuron_gpio_do_attrs, +}; + +static struct attribute_group neuron_gpio_ro_attr_group = { + .attrs = neuron_gpio_ro_attrs, +}; + +const struct attribute_group neuron_stm_ai_group = { + .attrs = neuron_stm_ai_attrs, +}; + +const struct attribute_group neuron_stm_ao_group = { + .attrs = neuron_stm_ao_attrs, +}; + +const struct attribute_group neuron_sec_ai_group = { + .attrs = neuron_sec_ai_attrs, +}; + +const struct attribute_group neuron_sec_ao_group = { + .attrs = neuron_sec_ao_attrs, +}; + +const struct attribute_group *neuron_plc_attr_groups[] = { + &neuron_plc_attr_group, + NULL, +}; + +const struct attribute_group *neuron_board_attr_groups[] = { + &neuron_board_attr_group, + NULL, +}; + +const struct attribute_group *neuron_gpio_di_attr_groups[] = { + &neuron_gpio_di_attr_group, + NULL, +}; + +const struct attribute_group *neuron_gpio_do_attr_groups[] = { + &neuron_gpio_do_attr_group, + NULL, +}; + +const struct attribute_group *neuron_gpio_ro_attr_groups[] = { + &neuron_gpio_ro_attr_group, + NULL, +}; diff --git a/modules/neuron_spi/src/unipi_sysfs.h b/modules/neuron_spi/src/unipi_sysfs.h index f4fa30b..4094912 100644 --- a/modules/neuron_spi/src/unipi_sysfs.h +++ b/modules/neuron_spi/src/unipi_sysfs.h @@ -42,235 +42,15 @@ #include "unipi_common.h" #include "unipi_platform.h" -ssize_t neuronspi_show_model(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_show_eeprom(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_show_regmap(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_store_regmap(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_show_serial(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_board(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_lboard_id(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_uboard_id(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_hw_version(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_hw_flash_version(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_fw_version(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_uart_queue_length(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_show_uart_config(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_store_uart_config(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_show_watchdog_status(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_store_watchdog_status(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_show_watchdog_timeout(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_store_watchdog_timeout(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_show_pwm_freq(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_store_pwm_freq(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_di_show_counter(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_di_store_counter(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_di_show_debounce(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_di_store_debounce(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_show_pwm_cycle(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_store_pwm_cycle(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_show_pwm_presc(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_store_pwm_presc(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_store_ds_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_store_ds_toggle(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_store_ds_polarity(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_show_ds_enable(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_ds_toggle(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_ds_polarity(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_do_prefix(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_do_base(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_do_count(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_di_prefix(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_di_base(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_di_count(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_ro_prefix(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_ro_base(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_show_ro_count(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_di_show_value(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_do_show_value(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_do_store_value(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_spi_gpio_ro_show_value(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_spi_gpio_ro_store_value(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_iio_show_primary_ai_mode(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_iio_store_primary_ai_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_iio_show_primary_ao_mode(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_iio_store_primary_ao_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_iio_show_secondary_ai_mode(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_iio_store_secondary_ai_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); -ssize_t neuronspi_iio_show_secondary_ao_mode(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t neuronspi_iio_store_secondary_ao_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); - -static DEVICE_ATTR(model_name, 0440, neuronspi_show_model, NULL); -static DEVICE_ATTR(sys_eeprom_name, 0440, neuronspi_show_eeprom, NULL); -static DEVICE_ATTR(register_read, 0660, neuronspi_show_regmap, neuronspi_store_regmap); -static DEVICE_ATTR(sys_board_serial, 0440, neuronspi_spi_show_serial, NULL); -static DEVICE_ATTR(sys_board_name, 0440, neuronspi_spi_show_board, NULL); -static DEVICE_ATTR(sys_primary_major_id, 0440, neuronspi_spi_show_lboard_id, NULL); -static DEVICE_ATTR(sys_secondary_major_id, 0440, neuronspi_spi_show_uboard_id, NULL); -static DEVICE_ATTR(sys_primary_minor_id, 0440, neuronspi_spi_show_hw_version, NULL); -static DEVICE_ATTR(sys_secondary_minor_id, 0440, neuronspi_spi_show_hw_flash_version, NULL); -static DEVICE_ATTR(firmware_version, 0440, neuronspi_spi_show_fw_version, NULL); -static DEVICE_ATTR(watchdog_status, 0660, neuronspi_spi_show_watchdog_status, neuronspi_spi_store_watchdog_status); -static DEVICE_ATTR(watchdog_timeout, 0660, neuronspi_spi_show_watchdog_timeout, neuronspi_spi_store_watchdog_timeout); -static DEVICE_ATTR(sys_gpio_do_count, 0440, neuronspi_spi_gpio_show_do_count, NULL); -static DEVICE_ATTR(sys_gpio_do_prefix, 0440, neuronspi_spi_gpio_show_do_prefix, NULL); -static DEVICE_ATTR(sys_gpio_do_base, 0440, neuronspi_spi_gpio_show_do_base, NULL); -static DEVICE_ATTR(sys_gpio_di_count, 0440, neuronspi_spi_gpio_show_di_count, NULL); -static DEVICE_ATTR(sys_gpio_di_prefix, 0440, neuronspi_spi_gpio_show_di_prefix, NULL); -static DEVICE_ATTR(ro_value, 0660, neuronspi_spi_gpio_ro_show_value, neuronspi_spi_gpio_ro_store_value); -static DEVICE_ATTR(do_value, 0660, neuronspi_spi_gpio_do_show_value, neuronspi_spi_gpio_do_store_value); -static DEVICE_ATTR(counter, 0660, neuronspi_spi_gpio_di_show_counter, neuronspi_spi_gpio_di_store_counter); -static DEVICE_ATTR(debounce, 0660, neuronspi_spi_gpio_di_show_debounce, neuronspi_spi_gpio_di_store_debounce); -static DEVICE_ATTR(di_value, 0440, neuronspi_spi_gpio_di_show_value, NULL); -static DEVICE_ATTR(direct_switch_enable, 0660, neuronspi_spi_gpio_show_ds_enable, neuronspi_spi_gpio_store_ds_enable); -static DEVICE_ATTR(direct_switch_toggle, 0660, neuronspi_spi_gpio_show_ds_toggle, neuronspi_spi_gpio_store_ds_toggle); -static DEVICE_ATTR(direct_switch_polarity, 0660, neuronspi_spi_gpio_show_ds_polarity, neuronspi_spi_gpio_store_ds_polarity); -static DEVICE_ATTR(pwm_frequency_cycle, 0660, neuronspi_spi_gpio_show_pwm_freq, neuronspi_spi_gpio_store_pwm_freq); -static DEVICE_ATTR(pwm_prescale, 0660, neuronspi_spi_gpio_show_pwm_presc, neuronspi_spi_gpio_store_pwm_presc); -static DEVICE_ATTR(pwm_duty_cycle, 0660, neuronspi_spi_gpio_show_pwm_cycle, neuronspi_spi_gpio_store_pwm_cycle); -static DEVICE_ATTR(uart_queue_length, 0440, neuronspi_spi_show_uart_queue_length, NULL); -static DEVICE_ATTR(uart_config, 0660, neuronspi_spi_show_uart_config, neuronspi_spi_store_uart_config); -static DEVICE_ATTR(sys_gpio_di_base, 0440, neuronspi_spi_gpio_show_di_base, NULL); -static DEVICE_ATTR(sys_gpio_ro_count, 0440, neuronspi_spi_gpio_show_ro_count, NULL); -static DEVICE_ATTR(sys_gpio_ro_prefix, 0440, neuronspi_spi_gpio_show_ro_prefix, NULL); -static DEVICE_ATTR(sys_gpio_ro_base, 0440, neuronspi_spi_gpio_show_ro_base, NULL); -static DEVICE_ATTR(mode_ai_type_a, 0660, neuronspi_iio_show_primary_ai_mode, neuronspi_iio_store_primary_ai_mode); -static DEVICE_ATTR(mode_ao_type_a, 0660, neuronspi_iio_show_primary_ao_mode, neuronspi_iio_store_primary_ao_mode); -static DEVICE_ATTR(mode_ai_type_b, 0660, neuronspi_iio_show_secondary_ai_mode, neuronspi_iio_store_secondary_ai_mode); -static DEVICE_ATTR(mode_ao_type_b, 0660, neuronspi_iio_show_secondary_ao_mode, neuronspi_iio_store_secondary_ao_mode); - -static struct attribute *neuron_plc_attrs[] = { - &dev_attr_model_name.attr, - &dev_attr_sys_eeprom_name.attr, - NULL, -}; - -static struct attribute *neuron_board_attrs[] = { - &dev_attr_sys_board_name.attr, - &dev_attr_sys_primary_major_id.attr, - &dev_attr_sys_secondary_major_id.attr, - &dev_attr_sys_primary_minor_id.attr, - &dev_attr_sys_secondary_minor_id.attr, - &dev_attr_firmware_version.attr, - &dev_attr_watchdog_status.attr, - &dev_attr_watchdog_timeout.attr, - &dev_attr_sys_board_serial.attr, - &dev_attr_uart_queue_length.attr, - &dev_attr_uart_config.attr, - &dev_attr_register_read.attr, - NULL, -}; - -static struct attribute *neuron_gpio_di_attrs[] = { - &dev_attr_sys_gpio_di_count.attr, - &dev_attr_sys_gpio_di_prefix.attr, - &dev_attr_sys_gpio_di_base.attr, - &dev_attr_direct_switch_enable.attr, - &dev_attr_direct_switch_toggle.attr, - &dev_attr_direct_switch_polarity.attr, - &dev_attr_di_value.attr, - &dev_attr_counter.attr, - &dev_attr_debounce.attr, - NULL, -}; - -static struct attribute *neuron_gpio_do_attrs[] = { - &dev_attr_sys_gpio_do_count.attr, - &dev_attr_sys_gpio_do_prefix.attr, - &dev_attr_sys_gpio_do_base.attr, - &dev_attr_pwm_frequency_cycle.attr, - &dev_attr_pwm_prescale.attr, - &dev_attr_pwm_duty_cycle.attr, - &dev_attr_do_value.attr, - NULL, -}; - -static struct attribute *neuron_gpio_ro_attrs[] = { - &dev_attr_sys_gpio_ro_count.attr, - &dev_attr_sys_gpio_ro_prefix.attr, - &dev_attr_sys_gpio_ro_base.attr, - &dev_attr_ro_value.attr, - NULL, -}; - -static struct attribute *neuron_stm_ai_attrs[] = { - &dev_attr_mode_ai_type_a.attr, - NULL, -}; - -static struct attribute *neuron_stm_ao_attrs[] = { - &dev_attr_mode_ao_type_a.attr, - NULL, -}; - -static struct attribute *neuron_sec_ai_attrs[] = { - &dev_attr_mode_ai_type_b.attr, - NULL, -}; - -static struct attribute *neuron_sec_ao_attrs[] = { - &dev_attr_mode_ao_type_b.attr, - NULL, -}; - -static struct attribute_group neuron_plc_attr_group = { - .attrs = neuron_plc_attrs, -}; - -static struct attribute_group neuron_board_attr_group = { - .attrs = neuron_board_attrs, -}; - -static struct attribute_group neuron_gpio_di_attr_group = { - .attrs = neuron_gpio_di_attrs, -}; - -static struct attribute_group neuron_gpio_do_attr_group = { - .attrs = neuron_gpio_do_attrs, -}; - -static struct attribute_group neuron_gpio_ro_attr_group = { - .attrs = neuron_gpio_ro_attrs, -}; - -static struct attribute_group neuron_stm_ai_group = { - .attrs = neuron_stm_ai_attrs, -}; - -static struct attribute_group neuron_stm_ao_group = { - .attrs = neuron_stm_ao_attrs, -}; - -static struct attribute_group neuron_sec_ai_group = { - .attrs = neuron_sec_ai_attrs, -}; - -static struct attribute_group neuron_sec_ao_group = { - .attrs = neuron_sec_ao_attrs, -}; - -static const struct attribute_group *neuron_plc_attr_groups[] = { - &neuron_plc_attr_group, - NULL, -}; - -static const struct attribute_group *neuron_board_attr_groups[] = { - &neuron_board_attr_group, - NULL, -}; - -static const struct attribute_group *neuron_gpio_di_attr_groups[] = { - &neuron_gpio_di_attr_group, - NULL, -}; - -static const struct attribute_group *neuron_gpio_do_attr_groups[] = { - &neuron_gpio_do_attr_group, - NULL, -}; - -static const struct attribute_group *neuron_gpio_ro_attr_groups[] = { - &neuron_gpio_ro_attr_group, - NULL, -}; +extern const struct attribute_group neuron_stm_ai_group; +extern const struct attribute_group neuron_stm_ao_group; +extern const struct attribute_group neuron_sec_ai_group; +extern const struct attribute_group neuron_sec_ao_group; + +extern const struct attribute_group *neuron_plc_attr_groups[]; +extern const struct attribute_group *neuron_board_attr_groups[]; +extern const struct attribute_group *neuron_gpio_di_attr_groups[]; +extern const struct attribute_group *neuron_gpio_do_attr_groups[]; +extern const struct attribute_group *neuron_gpio_ro_attr_groups[]; #endif /* MODULES_NEURON_SPI_SRC_UNIPI_SYSFS_H_ */ diff --git a/modules/neuron_spi/src/unipi_uart.c b/modules/neuron_spi/src/unipi_uart.c index 90200f7..32e8407 100644 --- a/modules/neuron_spi/src/unipi_uart.c +++ b/modules/neuron_spi/src/unipi_uart.c @@ -16,6 +16,10 @@ #include "unipi_uart.h" #include "unipi_spi.h" +struct neuronspi_uart_data* neuronspi_uart_glob_data; +unsigned long neuronspi_lines; +struct uart_driver* neuronspi_uart; + void neuronspi_uart_tx_proc(struct kthread_work *ws) { struct neuronspi_port *port = to_neuronspi_port(ws, tx_work); diff --git a/modules/neuron_spi/src/unipi_uart.h b/modules/neuron_spi/src/unipi_uart.h index fcedc87..cb0ec4c 100644 --- a/modules/neuron_spi/src/unipi_uart.h +++ b/modules/neuron_spi/src/unipi_uart.h @@ -42,6 +42,11 @@ #include "unipi_common.h" #include "unipi_platform.h" + +extern struct neuronspi_uart_data* neuronspi_uart_glob_data; +extern unsigned long neuronspi_lines; +extern struct uart_driver* neuronspi_uart; + void neuronspi_uart_start_tx(struct uart_port *port); void neuronspi_uart_stop_tx(struct uart_port *port); void neuronspi_uart_stop_rx(struct uart_port *port); -- 2.34.1